View | Details | Raw Unified | Return to bug 113482
Collapse All | Expand All

(-)cad/freehdl/Makefile (-1 / +2 lines)
Lines 9-15 Link Here
9
PORTVERSION=	0.0.4
9
PORTVERSION=	0.0.4
10
PORTREVISION=	1
10
PORTREVISION=	1
11
CATEGORIES=	cad
11
CATEGORIES=	cad
12
MASTER_SITES=	http://cran.mit.edu/~enaroska/
12
MASTER_SITES=	http://www.home.hs-karlsruhe.de/~fado0011/ \
13
		http://cran.mit.edu/~enaroska/
13
14
14
MAINTAINER=	lon_kamikaze@gmx.de
15
MAINTAINER=	lon_kamikaze@gmx.de
15
COMMENT=	A free VHDL simulator
16
COMMENT=	A free VHDL simulator

Return to bug 113482