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Lines 96-104
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| 96 |
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96 |
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| 97 |
switch (scp->chiptype) { |
97 |
switch (scp->chiptype) { |
| 98 |
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98 |
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99 |
case 0x24118086: /* Intel ICH */ |
| 100 |
if (udmamode >= 4) { |
| 101 |
int32_t mask48, new48, new54; |
| 102 |
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| 103 |
new54 = pci_read_config(parent, 0x54, 2); |
| 104 |
if (new54 & ( 1<< (devno+4))) { |
| 105 |
error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, |
| 106 |
ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); |
| 107 |
if (bootverbose) |
| 108 |
ata_printf(scp, device, "ICH setting up UDMA4 mode on %s chip\n", |
| 109 |
(error) ? "failed" : "success"); |
| 110 |
if (!error) { |
| 111 |
mask48 = (1 << devno) + (3 << (16 + (devno << 2))); |
| 112 |
new48 = (1 << devno) + (2 << (16 + (devno << 2))); |
| 113 |
pci_write_config(parent, 0x48, |
| 114 |
(pci_read_config(parent, 0x48, 4) & |
| 115 |
~mask48) | new48, 4); |
| 116 |
pci_write_config(parent, 0x54, new54 | (1 << devno), 2); |
| 117 |
scp->mode[ATA_DEV(device)] = ATA_UDMA4; |
| 118 |
return; |
| 119 |
} |
| 120 |
} |
| 121 |
} |
| 122 |
/* FALLTHROUGH */ |
| 123 |
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| 99 |
case 0x71118086: /* Intel PIIX4 */ |
124 |
case 0x71118086: /* Intel PIIX4 */ |
| 100 |
case 0x71998086: /* Intel PIIX4e */ |
125 |
case 0x71998086: /* Intel PIIX4e */ |
| 101 |
case 0x24118086: /* Intel ICH */ |
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| 102 |
case 0x24218086: /* Intel ICH0 */ |
126 |
case 0x24218086: /* Intel ICH0 */ |
| 103 |
if (udmamode >= 2) { |
127 |
if (udmamode >= 2) { |
| 104 |
int32_t mask48, new48; |
128 |
int32_t mask48, new48; |