|
Lines 342-347
Link Here
|
| 342 |
"do not m_devget() in dc driver"); |
342 |
"do not m_devget() in dc driver"); |
| 343 |
#endif |
343 |
#endif |
| 344 |
|
344 |
|
|
|
345 |
SYSCTL_NODE(_hw, OID_AUTO, dc, CTLFLAG_RD, 0, "if_dc parameters"); |
| 346 |
|
| 347 |
static int dc_ints; |
| 348 |
SYSCTL_INT(_hw_dc, OID_AUTO, ints, CTLFLAG_RW, &dc_ints, 0, ""); |
| 349 |
|
| 350 |
static int dc_isr_abnormal; |
| 351 |
SYSCTL_INT(_hw_dc, OID_AUTO, abnormal, CTLFLAG_RW, &dc_isr_abnormal, 0, ""); |
| 352 |
|
| 353 |
static int dc_isr_bus_err; |
| 354 |
SYSCTL_INT(_hw_dc, OID_AUTO, bus_err, CTLFLAG_RW, &dc_isr_bus_err, 0, ""); |
| 355 |
|
| 356 |
static int dc_isr_normal; |
| 357 |
SYSCTL_INT(_hw_dc, OID_AUTO, normal, CTLFLAG_RW, &dc_isr_normal, 0, ""); |
| 358 |
|
| 359 |
static int dc_isr_rx_nobuf; |
| 360 |
SYSCTL_INT(_hw_dc, OID_AUTO, rx_nobuf, CTLFLAG_RW, &dc_isr_rx_nobuf, 0, ""); |
| 361 |
|
| 362 |
static int dc_isr_rx_ok; |
| 363 |
SYSCTL_INT(_hw_dc, OID_AUTO, rx_ok, CTLFLAG_RW, &dc_isr_rx_ok, 0, ""); |
| 364 |
|
| 365 |
static int dc_isr_rx_watdogtimeo; |
| 366 |
SYSCTL_INT(_hw_dc, OID_AUTO, rx_watdogtimeo, CTLFLAG_RW, &dc_isr_rx_watdogtimeo, 0, ""); |
| 367 |
|
| 368 |
static int dc_isr_tx_idle; |
| 369 |
SYSCTL_INT(_hw_dc, OID_AUTO, tx_idle, CTLFLAG_RW, &dc_isr_tx_idle, 0, ""); |
| 370 |
|
| 371 |
static int dc_isr_tx_nobuf; |
| 372 |
SYSCTL_INT(_hw_dc, OID_AUTO, tx_nobuf, CTLFLAG_RW, &dc_isr_tx_nobuf, 0, ""); |
| 373 |
|
| 374 |
static int dc_isr_tx_ok; |
| 375 |
SYSCTL_INT(_hw_dc, OID_AUTO, tx_ok, CTLFLAG_RW, &dc_isr_tx_ok, 0, ""); |
| 376 |
|
| 377 |
static int dc_isr_tx_underrun; |
| 378 |
SYSCTL_INT(_hw_dc, OID_AUTO, tx_underrun, CTLFLAG_RW, &dc_isr_tx_underrun, 0, ""); |
| 379 |
|
| 380 |
static int dc_rx_resync1; |
| 381 |
SYSCTL_INT(_hw_dc, OID_AUTO, resync1, CTLFLAG_RW, &dc_rx_resync1, 0, ""); |
| 382 |
|
| 383 |
static int dc_rx_resync2; |
| 384 |
SYSCTL_INT(_hw_dc, OID_AUTO, resync2, CTLFLAG_RW, &dc_rx_resync2, 0, ""); |
| 385 |
|
| 345 |
DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); |
386 |
DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); |
| 346 |
DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); |
387 |
DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); |
| 347 |
DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); |
388 |
DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); |
|
Lines 3097-3122
Link Here
|
| 3097 |
/* Disable interrupts. */ |
3138 |
/* Disable interrupts. */ |
| 3098 |
CSR_WRITE_4(sc, DC_IMR, 0x00000000); |
3139 |
CSR_WRITE_4(sc, DC_IMR, 0x00000000); |
| 3099 |
|
3140 |
|
|
|
3141 |
dc_ints++; |
| 3142 |
|
| 3100 |
while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && |
3143 |
while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && |
| 3101 |
status != 0xFFFFFFFF && |
3144 |
status != 0xFFFFFFFF && |
| 3102 |
(ifp->if_drv_flags & IFF_DRV_RUNNING)) { |
3145 |
(ifp->if_drv_flags & IFF_DRV_RUNNING)) { |
| 3103 |
|
3146 |
|
| 3104 |
CSR_WRITE_4(sc, DC_ISR, status); |
3147 |
CSR_WRITE_4(sc, DC_ISR, status); |
| 3105 |
|
3148 |
|
|
|
3149 |
if (status & DC_ISR_ABNORMAL) |
| 3150 |
dc_isr_abnormal++; |
| 3151 |
if (status & DC_ISR_NORMAL) |
| 3152 |
dc_isr_normal++; |
| 3153 |
|
| 3106 |
if (status & DC_ISR_RX_OK) { |
3154 |
if (status & DC_ISR_RX_OK) { |
| 3107 |
int curpkts; |
3155 |
int curpkts; |
|
|
3156 |
|
| 3157 |
dc_isr_rx_ok++; |
| 3108 |
curpkts = ifp->if_ipackets; |
3158 |
curpkts = ifp->if_ipackets; |
| 3109 |
dc_rxeof(sc); |
3159 |
dc_rxeof(sc); |
| 3110 |
if (curpkts == ifp->if_ipackets) { |
3160 |
if (curpkts == ifp->if_ipackets) { |
| 3111 |
while (dc_rx_resync(sc)) |
3161 |
while (dc_rx_resync(sc)) { |
|
|
3162 |
dc_rx_resync1++; |
| 3112 |
dc_rxeof(sc); |
3163 |
dc_rxeof(sc); |
|
|
3164 |
} |
| 3113 |
} |
3165 |
} |
| 3114 |
} |
3166 |
} |
| 3115 |
|
3167 |
|
| 3116 |
if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) |
3168 |
if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) { |
|
|
3169 |
if (status & DC_ISR_TX_OK) |
| 3170 |
dc_isr_tx_ok++; |
| 3171 |
if (status & DC_ISR_TX_NOBUF) |
| 3172 |
dc_isr_tx_nobuf++; |
| 3117 |
dc_txeof(sc); |
3173 |
dc_txeof(sc); |
|
|
3174 |
} |
| 3118 |
|
3175 |
|
| 3119 |
if (status & DC_ISR_TX_IDLE) { |
3176 |
if (status & DC_ISR_TX_IDLE) { |
|
|
3177 |
dc_isr_tx_idle++; |
| 3120 |
dc_txeof(sc); |
3178 |
dc_txeof(sc); |
| 3121 |
if (sc->dc_cdata.dc_tx_cnt) { |
3179 |
if (sc->dc_cdata.dc_tx_cnt) { |
| 3122 |
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); |
3180 |
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); |
|
Lines 3124-3144
Link Here
|
| 3124 |
} |
3182 |
} |
| 3125 |
} |
3183 |
} |
| 3126 |
|
3184 |
|
| 3127 |
if (status & DC_ISR_TX_UNDERRUN) |
3185 |
if (status & DC_ISR_TX_UNDERRUN) { |
|
|
3186 |
dc_isr_tx_underrun++; |
| 3128 |
dc_tx_underrun(sc); |
3187 |
dc_tx_underrun(sc); |
|
|
3188 |
} |
| 3129 |
|
3189 |
|
| 3130 |
if ((status & DC_ISR_RX_WATDOGTIMEO) |
3190 |
if ((status & DC_ISR_RX_WATDOGTIMEO) |
| 3131 |
|| (status & DC_ISR_RX_NOBUF)) { |
3191 |
|| (status & DC_ISR_RX_NOBUF)) { |
| 3132 |
int curpkts; |
3192 |
int curpkts; |
|
|
3193 |
if (status & DC_ISR_RX_WATDOGTIMEO) |
| 3194 |
dc_isr_rx_watdogtimeo++; |
| 3195 |
if (status & DC_ISR_RX_NOBUF) |
| 3196 |
dc_isr_rx_nobuf++; |
| 3133 |
curpkts = ifp->if_ipackets; |
3197 |
curpkts = ifp->if_ipackets; |
| 3134 |
dc_rxeof(sc); |
3198 |
dc_rxeof(sc); |
| 3135 |
if (curpkts == ifp->if_ipackets) { |
3199 |
if (curpkts == ifp->if_ipackets) { |
| 3136 |
while (dc_rx_resync(sc)) |
3200 |
while (dc_rx_resync(sc)) { |
|
|
3201 |
dc_rx_resync2++; |
| 3137 |
dc_rxeof(sc); |
3202 |
dc_rxeof(sc); |
|
|
3203 |
} |
| 3138 |
} |
3204 |
} |
| 3139 |
} |
3205 |
} |
| 3140 |
|
3206 |
|
| 3141 |
if (status & DC_ISR_BUS_ERR) { |
3207 |
if (status & DC_ISR_BUS_ERR) { |
|
|
3208 |
dc_isr_bus_err++; |
| 3142 |
dc_reset(sc); |
3209 |
dc_reset(sc); |
| 3143 |
dc_init_locked(sc); |
3210 |
dc_init_locked(sc); |
| 3144 |
} |
3211 |
} |