Attachment #8395 for bug #17601

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Lines 43-49 Link Here

(-)if_tx.c (-115 / +118 lines)
43		43
44	/* We should define compile time options before if_txvar.h included */	44	/* We should define compile time options before if_txvar.h included */
45	/#define EPIC_NOIFMEDIA 1/	45	/#define EPIC_NOIFMEDIA 1/
46	/#define EPIC_USEIOSPACE 1/
47	#define EARLY_RX 1	46	#define EARLY_RX 1
48	/#define EPIC_DEBUG 1/	47	/#define EPIC_DEBUG 1/
49		48
Lines 65-71 Link Here
65	} \	64	} \
66	}	65	}
67		66
		67	#if defined(__FreeBSD__)
		68	#define NBPF 1
		69	#else
68	#include "bpf.h"	70	#include "bpf.h"
		71	#endif
69	#include "opt_bdg.h"	72	#include "opt_bdg.h"
70		73
71	#include <sys/param.h>	74	#include <sys/param.h>
Lines 123-128 Link Here
123		126
124	#include <dev/pci/if_txvar.h>	127	#include <dev/pci/if_txvar.h>
125	#else /* __FreeBSD__ */	128	#else /* __FreeBSD__ */
		129	#include <sys/bus.h>
		130	#include <machine/bus.h>
		131	#include <sys/rman.h>
		132	#include <machine/resource.h>
		133
126	#include <sys/eventhandler.h>	134	#include <sys/eventhandler.h>
127	#include <net/if_mib.h>	135	#include <net/if_mib.h>
128	#include <netinet/in.h>	136	#include <netinet/in.h>
Lines 132-137 Link Here
132	#include <machine/clock.h>	140	#include <machine/clock.h>
133		141
134	#include <pci/pcivar.h>	142	#include <pci/pcivar.h>
		143	#include <pci/pcireg.h>
135	#include <pci/if_txvar.h>	144	#include <pci/if_txvar.h>
136		145
137	#ifdef BRIDGE	146	#ifdef BRIDGE
Lines 375-444 Link Here
375	#else /* __FreeBSD__ */	384	#else /* __FreeBSD__ */
376	/* -----------------------------FreeBSD------------------------------------- */	385	/* -----------------------------FreeBSD------------------------------------- */
377		386
		387	/*
378	static const char* epic_freebsd_probe __P((pcici_t, pcidi_t));	388	static const char* epic_freebsd_probe __P((pcici_t, pcidi_t));
379	static void epic_freebsd_attach __P((pcici_t, int));	389	static void epic_freebsd_attach __P((pcici_t, int));
380	static void epic_shutdown __P((void *, int));	390	static void epic_shutdown __P((void *));
381		391	*/
382	/* Global variables */
383	static u_long epic_pci_count;
384	static struct pci_device txdevice = {
385	"tx",
386	epic_freebsd_probe,
387	epic_freebsd_attach,
388	&epic_pci_count,
389	NULL
390	};
391
392	/* Append this driver to pci drivers list */
393	COMPAT_PCI_DRIVER (tx, txdevice);
394		392
395	/* Synopsis: Check if device id corresponds with SMC83C170 id. */	393	/* Synopsis: Check if device id corresponds with SMC83C170 id. */
396	static const char*	394	static int
397	epic_freebsd_probe(	395	epic_freebsd_probe(device_t dev)
398	pcici_t config_id,
399	pcidi_t device_id)
400	{	396	{
401	if( PCI_VENDORID(device_id) != SMC_VENDORID )	397	if ((pci_get_vendor(dev) == SMC_VENDORID) &&
402	return NULL;	398	(pci_get_device(dev) == CHIPID_83C170)) {
403		399	device_set_desc(dev, "SMC 83c170");
404	if( PCI_CHIPID(device_id) == CHIPID_83C170 )	400	return 0;
405	return "SMC 83c170";	401	}
406		402
407	return NULL;	403	return ENXIO;
408	}	404	}
409		405
410	/*	406	/*
411	* Do FreeBSD-specific attach routine, like map registers, alloc softc	407	* Do FreeBSD-specific attach routine, like map registers, alloc softc
412	* structure and etc.	408	* structure and etc.
413	*/	409	*/
414	static void	410	static int
415	epic_freebsd_attach(	411	epic_freebsd_attach(device_t dev)
416	pcici_t config_id,
417	int unit)
418	{	412	{
419	struct ifnet *ifp;	413	struct ifnet *ifp;
420	epic_softc_t *sc;	414	epic_softc_t *sc = device_get_softc(dev);
421	#if defined(EPIC_USEIOSPACE)
422	u_int32_t iobase;
423	#else
424	caddr_t pmembase;
425	#endif
426	u_int32_t command;	415	u_int32_t command;
427	int i,s,tmp;	416	int i,s,tmp;
		417	int rid;
428		418
429	printf("tx%d",unit);
430
431	/* Allocate memory for softc, hardware descriptors and frag lists */
432	sc = (epic_softc_t *) malloc( sizeof(epic_softc_t), M_DEVBUF, M_NOWAIT);
433	if (sc == NULL) return;
434
435	/* Preinitialize softc structure */
436	bzero(sc, sizeof(epic_softc_t));
437	sc->unit = unit;
438
439	/* Fill ifnet structure */	419	/* Fill ifnet structure */
440	ifp = &sc->sc_if;	420	ifp = &sc->sc_if;
441	ifp->if_unit = unit;	421	ifp->if_unit = device_get_unit(dev);
442	ifp->if_name = "tx";	422	ifp->if_name = "tx";
443	ifp->if_softc = sc;	423	ifp->if_softc = sc;
444	ifp->if_flags = IFF_BROADCAST\|IFF_SIMPLEX\|IFF_MULTICAST;	424	ifp->if_flags = IFF_BROADCAST\|IFF_SIMPLEX\|IFF_MULTICAST;
Lines 449-504 Link Here
449	ifp->if_timer = 0;	429	ifp->if_timer = 0;
450	ifp->if_output = ether_output;	430	ifp->if_output = ether_output;
451	ifp->if_snd.ifq_maxlen = TX_RING_SIZE;	431	ifp->if_snd.ifq_maxlen = TX_RING_SIZE;
452
453	/* Get iobase or membase */
454	#if defined(EPIC_USEIOSPACE)
455	command = PCI_CONF_READ(PCI_CFCS);
456	command \|= PCI_CFCS_IOEN;
457	PCI_CONF_WRITE(PCI_CFCS, command);
458	command = PCI_CONF_READ(PCI_CFCS);
459
460	if (!(command & PCI_CFCS_IOEN)) {
461	printf(": failed to enable memory mapping!\n");
462	free(sc, M_DEVBUF);
463	return;
464	}
465		432
466	if (!pci_map_port(config_id, PCI_CBIO,(u_short *) &(sc->iobase))) {	433	/* Get membase */
467	printf(": cannot map port\n");	434	command = pci_read_config(dev, PCIR_COMMAND, 2);
468	free(sc, M_DEVBUF);	435	command \|= PCIM_CMD_MEMEN;
469	return;	436	pci_write_config(dev, PCIR_COMMAND, command, 2);
470	}	437
471	#else	438	rid = PCI_CBMA;
472	command = PCI_CONF_READ(PCI_CFCS);	439	sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
473	command \|= PCI_CFCS_MAEN;	440	0, ~0, 1, RF_ACTIVE);
474	PCI_CONF_WRITE(PCI_CFCS, command);	441	if(!sc->mem) {
475	command = PCI_CONF_READ(PCI_CFCS);	442	device_printf(dev, "cannot map memory\n");
476		443	return ENXIO;
477	if (!(command & PCI_CFCS_MAEN)) {
478	printf(": failed to enable memory mapping!\n");
479	free(sc, M_DEVBUF);
480	return;
481	}	444	}
		445	sc->sc_st = rman_get_bustag(sc->mem);
		446	sc->sc_sh = rman_get_bushandle(sc->mem);
482		447
483	if (!pci_map_mem(config_id, PCI_CBMA,(vm_offset_t ) &(sc->csr),(vm_offset_t ) &pmembase)) {
484	printf(": cannot map memory\n");
485	free(sc, M_DEVBUF);
486	return;
487	}
488	#endif
489
490	/* Do OS independent part, including chip wakeup and reset */	448	/* Do OS independent part, including chip wakeup and reset */
491	if( epic_common_attach(sc) ) return;	449	if( epic_common_attach(sc) ) return ENXIO;
492		450
493	/* Enable BusMaster'ing */	451	/* Enable BusMaster'ing */
494	command = PCI_CONF_READ(PCI_CFCS);	452	command = pci_read_config(dev, PCIR_COMMAND, 2);
495	command \|= PCI_CFCS_BMEN;	453	command \|= PCIM_CMD_BUSMASTEREN;
496	PCI_CONF_WRITE(PCI_CFCS, command);	454	pci_write_config(dev, PCIR_COMMAND, command, 2);
497		455
498	/* Display ethernet address ,... */	456	/* Display ethernet address ,... */
499	printf(": address %02x:%02x:%02x:%02x:%02x:%02x,",	457	device_printf(dev, "address %6D,", sc->sc_macaddr, ":");
500	sc->sc_macaddr[0],sc->sc_macaddr[1],sc->sc_macaddr[2],
501	sc->sc_macaddr[3],sc->sc_macaddr[4],sc->sc_macaddr[5]);
502		458
503	/* board type and ... */	459	/* board type and ... */
504	printf(" type ");	460	printf(" type ");
Lines 567-605 Link Here
567	s = splimp();	523	s = splimp();
568		524
569	/* Map interrupt */	525	/* Map interrupt */
570	if( !pci_map_int(config_id, epic_intr, (void*)sc, &net_imask) ) {	526	rid = 0;
571	printf(": couldn't map interrupt\n");	527	sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
572	free(sc, M_DEVBUF);	528	RF_SHAREABLE \| RF_ACTIVE);
573	return;	529	if (sc->irq == NULL) {
		530	device_printf(dev, "couldn't map iterrupt\n");
		531	splx(s);
		532	return ENXIO;
		533	}
		534	tmp = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
		535	epic_intr, sc, &sc->sc_ih);
		536	if (tmp) {
		537	device_printf(dev, "couldn't setup irq\n");
		538	splx(s);
		539	return tmp;
574	}	540	}
575		541
576	/* Set shut down routine to stop DMA processes on reboot */
577	EVENTHANDLER_REGISTER(shutdown_post_sync, epic_shutdown, sc,
578	SHUTDOWN_PRI_DEFAULT);
579
580	/* Attach to if manager */	542	/* Attach to if manager */
581	if_attach(ifp);	543	if_attach(ifp);
582	ether_ifattach(ifp);	544	ether_ifattach(ifp);
583
584	#if NBPF > 0
585	bpfattach(ifp,DLT_EN10MB, sizeof(struct ether_header));	545	bpfattach(ifp,DLT_EN10MB, sizeof(struct ether_header));
586	#endif
587		546
588	splx(s);	547	splx(s);
589		548
590	printf("\n");	549	printf("\n");
591		550
592	return;	551	return 0;
593	}	552	}
594		553
595	static void	554	static int
596	epic_shutdown(	555	epic_freebsd_detach(device_t dev)
597	void *sc,
598	int howto)
599	{	556	{
		557	epic_softc_t *sc = device_get_softc(dev);
		558	int s;
		559
		560	s = splimp();
		561
		562	/*
		563	* Close down routes etc.
		564	*/
		565	bpfdetach(&sc->arpcom.ac_if);
		566	if_detach(&sc->arpcom.ac_if);
		567
		568	/*
		569	* Stop DMA and drop transmit queue.
		570	*/
600	epic_stop(sc);	571	epic_stop(sc);
		572
		573	/*
		574	* Dellocate resources.
		575	*/
		576	bus_teardown_intr(dev, sc->irq, sc->sc_ih);
		577	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
		578	bus_release_resource(dev, SYS_RES_MEMORY, PCI_CBMA, sc->mem);
		579
		580	/*
		581	* XXX free more resources.
		582	*/
		583
		584	return 0;
		585	}
		586
		587	static int
		588	epic_shutdown(device_t dev)
		589	{
		590	epic_stop((epic_softc_t *) device_get_softc(dev));
		591	return 0;
601	}	592	}
602		593
		594	static device_method_t epic_methods[] = {
		595	/* Device iterface */
		596	DEVMETHOD(device_probe, epic_freebsd_probe),
		597	DEVMETHOD(device_attach, epic_freebsd_attach),
		598	DEVMETHOD(device_detach, epic_freebsd_detach),
		599	DEVMETHOD(device_shutdown, epic_shutdown),
		600
		601	{ 0, 0 }
		602	};
		603
		604	static driver_t epic_driver = {
		605	"tx",
		606	epic_methods,
		607	sizeof(epic_softc_t),
		608	};
		609
		610	static devclass_t epic_devclass;
		611
		612	DRIVER_MODULE(if_tx, pci, epic_driver, epic_devclass, 0, 0);
		613
603	#endif /* __OpenBSD__ */	614	#endif /* __OpenBSD__ */
604		615
605	/* ------------------------------------------------------------------------	616	/* ------------------------------------------------------------------------
Lines 879-889 Link Here
879		890
880	#if NBPF > 0	891	#if NBPF > 0
881	if( ifp->if_bpf )	892	if( ifp->if_bpf )
882	#if defined(__FreeBSD__)	893	bpf_mtap( EPIC_BPFTAP_ARG(ifp), m0 );
883	bpf_mtap( ifp, m0 );
884	#else /* __OpenBSD__ */
885	bpf_mtap( ifp->if_bpf, m0 );
886	#endif /* __FreeBSD__ */
887	#endif	894	#endif
888	}	895	}
889		896
Lines 947-960 Link Here
947	m->m_pkthdr.rcvif = &(sc->sc_if);	954	m->m_pkthdr.rcvif = &(sc->sc_if);
948	m->m_pkthdr.len = m->m_len = len;	955	m->m_pkthdr.len = m->m_len = len;
949		956
950	#if NBPF > 0
951	/* Give mbuf to BPF */	957	/* Give mbuf to BPF */
		958	#if NBPF > 0
952	if( sc->sc_if.if_bpf )	959	if( sc->sc_if.if_bpf )
953	#if defined(__FreeBSD__)	960	bpf_mtap( EPIC_BPFTAP_ARG(&sc->sc_if), m );
954	bpf_mtap( &sc->sc_if, m );
955	#else /* __OpenBSD__ */
956	bpf_mtap( sc->sc_if.if_bpf, m );
957	#endif /* __FreeBSD__ */
958	#endif /* NBPF */	961	#endif /* NBPF */
959		962
960	#ifdef BRIDGE	963	#ifdef BRIDGE




	struct arpcom		arpcom;
#if defined(__OpenBSD__)
	struct device		sc_dev;
#else /* __FreeBSD__ */
	struct resource		*mem;
	struct resource		*irq;
#endif
	void			*sc_ih;
	bus_space_tag_t		sc_st;
	bus_space_handle_t	sc_sh;
#else /* __FreeBSD__ */
#if defined(EPIC_USEIOSPACE)
	u_int32_t		iobase;
#else
	caddr_t			csr;
#endif
#endif
#if !defined(EPIC_NOIFMEDIA)
	struct ifmedia 		ifmedia;
#endif

#if defined(__FreeBSD__)
#define EPIC_FORMAT	"tx%d"
#define EPIC_ARGS(sc)	(sc->unit)
#define EPIC_BPFTAP_ARG(ifp)	ifp
#define sc_if arpcom.ac_if
#define sc_macaddr arpcom.ac_enaddr
#if defined(EPIC_USEIOSPACE)
#define CSR_WRITE_4(sc,reg,val) 					\
	outl( (sc)->iobase + (u_int32_t)(reg), (val) )
#define CSR_WRITE_2(sc,reg,val) 					\
	outw( (sc)->iobase + (u_int32_t)(reg), (val) )
#define CSR_WRITE_1(sc,reg,val) 					\
	outb( (sc)->iobase + (u_int32_t)(reg), (val) )
#define CSR_READ_4(sc,reg) 						\
	inl( (sc)->iobase + (u_int32_t)(reg) )
#define CSR_READ_2(sc,reg) 						\
	inw( (sc)->iobase + (u_int32_t)(reg) )
#define CSR_READ_1(sc,reg) 						\
	inb( (sc)->iobase + (u_int32_t)(reg) )
#else
#define CSR_WRITE_1(sc,reg,val) 					\
	((*(volatile u_int8_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int8_t)(val))
#define CSR_WRITE_2(sc,reg,val) 					\
	((*(volatile u_int16_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int16_t)(val))
#define CSR_WRITE_4(sc,reg,val) 					\
	((*(volatile u_int32_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int32_t)(val))
#define CSR_READ_1(sc,reg) 						\
	(*(volatile u_int8_t*)((sc)->csr + (u_int32_t)(reg)))
#define CSR_READ_2(sc,reg) 						\
	(*(volatile u_int16_t*)((sc)->csr + (u_int32_t)(reg)))
#define CSR_READ_4(sc,reg) 						\
	(*(volatile u_int32_t*)((sc)->csr + (u_int32_t)(reg)))
#endif
#else /* __OpenBSD__ */
#define EPIC_FORMAT	"%s"
#define EPIC_ARGS(sc)	(sc->sc_dev.dv_xname)
#define EPIC_BPFTAP_ARG(ifp)	(ifp)->if_bpf
#define sc_if	arpcom.ac_if
#define sc_macaddr arpcom.ac_enaddr
#endif
#define CSR_WRITE_4(sc,reg,val) 					\
	bus_space_write_4( (sc)->sc_st, (sc)->sc_sh, (reg), (val) )
#define CSR_WRITE_2(sc,reg,val) 					\

	bus_space_read_2( (sc)->sc_st, (sc)->sc_sh, (reg) )
#define CSR_READ_1(sc,reg) 						\
	bus_space_read_1( (sc)->sc_st, (sc)->sc_sh, (reg) )
#endif

#define	PHY_READ_2(sc,reg)	epic_read_phy_register(sc,reg)
#define PHY_WRITE_2(sc,reg,val)	epic_write_phy_register(sc,reg,val)

Return to bug 17601

Lines 330-345 Link Here

(-)if_txvar.h (-35 / +7 lines)
330	struct arpcom arpcom;	330	struct arpcom arpcom;
331	#if defined(__OpenBSD__)	331	#if defined(__OpenBSD__)
332	struct device sc_dev;	332	struct device sc_dev;
		333	#else /* __FreeBSD__ */
		334	struct resource *mem;
		335	struct resource *irq;
		336	#endif
333	void *sc_ih;	337	void *sc_ih;
334	bus_space_tag_t sc_st;	338	bus_space_tag_t sc_st;
335	bus_space_handle_t sc_sh;	339	bus_space_handle_t sc_sh;
336	#else /* __FreeBSD__ */
337	#if defined(EPIC_USEIOSPACE)
338	u_int32_t iobase;
339	#else
340	caddr_t csr;
341	#endif
342	#endif
343	#if !defined(EPIC_NOIFMEDIA)	340	#if !defined(EPIC_NOIFMEDIA)
344	struct ifmedia ifmedia;	341	struct ifmedia ifmedia;
345	#endif	342	#endif
Lines 366-405 Link Here
366	#if defined(__FreeBSD__)	363	#if defined(__FreeBSD__)
367	#define EPIC_FORMAT "tx%d"	364	#define EPIC_FORMAT "tx%d"
368	#define EPIC_ARGS(sc) (sc->unit)	365	#define EPIC_ARGS(sc) (sc->unit)
		366	#define EPIC_BPFTAP_ARG(ifp) ifp
369	#define sc_if arpcom.ac_if	367	#define sc_if arpcom.ac_if
370	#define sc_macaddr arpcom.ac_enaddr	368	#define sc_macaddr arpcom.ac_enaddr
371	#if defined(EPIC_USEIOSPACE)
372	#define CSR_WRITE_4(sc,reg,val) \
373	outl( (sc)->iobase + (u_int32_t)(reg), (val) )
374	#define CSR_WRITE_2(sc,reg,val) \
375	outw( (sc)->iobase + (u_int32_t)(reg), (val) )
376	#define CSR_WRITE_1(sc,reg,val) \
377	outb( (sc)->iobase + (u_int32_t)(reg), (val) )
378	#define CSR_READ_4(sc,reg) \
379	inl( (sc)->iobase + (u_int32_t)(reg) )
380	#define CSR_READ_2(sc,reg) \
381	inw( (sc)->iobase + (u_int32_t)(reg) )
382	#define CSR_READ_1(sc,reg) \
383	inb( (sc)->iobase + (u_int32_t)(reg) )
384	#else
385	#define CSR_WRITE_1(sc,reg,val) \
386	(((volatile u_int8_t)((sc)->csr + (u_int32_t)(reg))) = (u_int8_t)(val))
387	#define CSR_WRITE_2(sc,reg,val) \
388	(((volatile u_int16_t)((sc)->csr + (u_int32_t)(reg))) = (u_int16_t)(val))
389	#define CSR_WRITE_4(sc,reg,val) \
390	(((volatile u_int32_t)((sc)->csr + (u_int32_t)(reg))) = (u_int32_t)(val))
391	#define CSR_READ_1(sc,reg) \
392	((volatile u_int8_t)((sc)->csr + (u_int32_t)(reg)))
393	#define CSR_READ_2(sc,reg) \
394	((volatile u_int16_t)((sc)->csr + (u_int32_t)(reg)))
395	#define CSR_READ_4(sc,reg) \
396	((volatile u_int32_t)((sc)->csr + (u_int32_t)(reg)))
397	#endif
398	#else /* __OpenBSD__ */	369	#else /* __OpenBSD__ */
399	#define EPIC_FORMAT "%s"	370	#define EPIC_FORMAT "%s"
400	#define EPIC_ARGS(sc) (sc->sc_dev.dv_xname)	371	#define EPIC_ARGS(sc) (sc->sc_dev.dv_xname)
		372	#define EPIC_BPFTAP_ARG(ifp) (ifp)->if_bpf
401	#define sc_if arpcom.ac_if	373	#define sc_if arpcom.ac_if
402	#define sc_macaddr arpcom.ac_enaddr	374	#define sc_macaddr arpcom.ac_enaddr
		375	#endif
403	#define CSR_WRITE_4(sc,reg,val) \	376	#define CSR_WRITE_4(sc,reg,val) \
404	bus_space_write_4( (sc)->sc_st, (sc)->sc_sh, (reg), (val) )	377	bus_space_write_4( (sc)->sc_st, (sc)->sc_sh, (reg), (val) )
405	#define CSR_WRITE_2(sc,reg,val) \	378	#define CSR_WRITE_2(sc,reg,val) \
Lines 412-418 Link Here
412	bus_space_read_2( (sc)->sc_st, (sc)->sc_sh, (reg) )	385	bus_space_read_2( (sc)->sc_st, (sc)->sc_sh, (reg) )
413	#define CSR_READ_1(sc,reg) \	386	#define CSR_READ_1(sc,reg) \
414	bus_space_read_1( (sc)->sc_st, (sc)->sc_sh, (reg) )	387	bus_space_read_1( (sc)->sc_st, (sc)->sc_sh, (reg) )
415	#endif
416		388
417	#define PHY_READ_2(sc,reg) epic_read_phy_register(sc,reg)	389	#define PHY_READ_2(sc,reg) epic_read_phy_register(sc,reg)
418	#define PHY_WRITE_2(sc,reg,val) epic_write_phy_register(sc,reg,val)	390	#define PHY_WRITE_2(sc,reg,val) epic_write_phy_register(sc,reg,val)