Attachment #8623 for bug #17984

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	u_char	sv_pad[64];	/* padding; used by emulators */
};

/* Intel prefers long real (53 bit) precision */
#define	__iBCS_NPXCW__		0x262
/* wfj prefers temporary real (64 bit) precision */
#define	__386BSD_NPXCW__	0x362
/*
 * The hardware default control word for i387's and later coprocessors 
 * 0x37F, giving:
 * The standard control word from finit is 0x37F, giving:
 *
 *	round to nearest
 *	64-bit precision
 *	all exceptions masked.
 *
 * We modify the affine mode bit and precision bits in this to give:
 *
 *	affine mode for 287's (if they work at all) (1 in bitfield 1<<12)
 *	53-bit precision (2 in bitfield 3<<8)
 *	overflow exception unmasked (0 in bitfield 1<<3)
 *	zero divide exception unmasked (0 in bitfield 1<<2)
 *	invalid-operand exception unmasked (0 in bitfield 1<<0).
 *
 * 64-bit precision often gives bad results with high level languages
 * because it makes the results of calculations depend on whether
 * intermediate values are stored in memory or in FPU registers.
 *
 * The "Intel" and wfj control words have:
 *
 *	underflow exception unmasked (0 in bitfield 1<<4)
 *
 * but that causes an unexpected exception in the test program 
 * and makes denormals useless (DBL_MIN / 2 underflows).  It doesn't 
 * a lot of sense to trap underflow without trapping denormals.
 *
 * Later I will want the IEEE default of all exceptions masked.  See 
 * 0.0 math manpage for why this is better.  The 0.1 math manpage is 
 */
#define	__INITIAL_NPXCW__	0x127F
#define	__BETTER_BDE_NPXCW__	0x127f

#ifdef __BROKEN_NPXCW__
#ifdef __FreeBSD__
#define	__INITIAL_NPXCW__	__386BSD_NPXCW__
#else
#define	__INITIAL_NPXCW__	__iBCS_NPXCW__
#endif
#else
#define	__INITIAL_NPXCW__	__BDE_NPXCW__
#endif

#ifdef KERNEL
extern struct proc *npxproc;

Return to bug 17984

Lines 85-138 Link Here

(-)npx.h (-34 / +4 lines)
85	u_char sv_pad[64]; /* padding; used by emulators */	85	u_char sv_pad[64]; /* padding; used by emulators */
86	};	86	};
87		87
88	/* Intel prefers long real (53 bit) precision */
89	#define __iBCS_NPXCW__ 0x262
90	/* wfj prefers temporary real (64 bit) precision */
91	#define __386BSD_NPXCW__ 0x362
92	/*	88	/*
93	* bde prefers 53 bit precision and all exceptions masked.	89	* The hardware default control word for i387's and later coprocessors
94	*	90	* 0x37F, giving:
95	* The standard control word from finit is 0x37F, giving:
96	*	91	*
97	* round to nearest	92	* round to nearest
98	* 64-bit precision	93	* 64-bit precision
99	* all exceptions masked.	94	* all exceptions masked.
100	*	95	*
101	* Now I want:	96	* We modify the affine mode bit and precision bits in this to give:
102	*	97	*
103	* affine mode for 287's (if they work at all) (1 in bitfield 1<<12)	98	* affine mode for 287's (if they work at all) (1 in bitfield 1<<12)
104	* 53-bit precision (2 in bitfield 3<<8)	99	* 53-bit precision (2 in bitfield 3<<8)
105	* overflow exception unmasked (0 in bitfield 1<<3)
106	* zero divide exception unmasked (0 in bitfield 1<<2)
107	* invalid-operand exception unmasked (0 in bitfield 1<<0).
108	*	100	*
109	* 64-bit precision often gives bad results with high level languages	101	* 64-bit precision often gives bad results with high level languages
110	* because it makes the results of calculations depend on whether	102	* because it makes the results of calculations depend on whether
111	* intermediate values are stored in memory or in FPU registers.	103	* intermediate values are stored in memory or in FPU registers.
112	*
113	* The "Intel" and wfj control words have:
114	*
115	* underflow exception unmasked (0 in bitfield 1<<4)
116	*
117	* but that causes an unexpected exception in the test program
118	* and makes denormals useless (DBL_MIN / 2 underflows). It doesn't
119	* a lot of sense to trap underflow without trapping denormals.
120	*
121	* Later I will want the IEEE default of all exceptions masked. See
122	* 0.0 math manpage for why this is better. The 0.1 math manpage is
123	*/	104	*/
124	#define __BDE_NPXCW__ 0x1272	105	#define __INITIAL_NPXCW__ 0x127F
125	#define __BETTER_BDE_NPXCW__ 0x127f
126
127	#ifdef __BROKEN_NPXCW__
128	#ifdef __FreeBSD__
129	#define __INITIAL_NPXCW__ __386BSD_NPXCW__
130	#else
131	#define __INITIAL_NPXCW__ __iBCS_NPXCW__
132	#endif
133	#else
134	#define __INITIAL_NPXCW__ __BDE_NPXCW__
135	#endif
136		106
137	#ifdef KERNEL	107	#ifdef KERNEL
138	extern struct proc *npxproc;	108	extern struct proc *npxproc;