| Summary: | ASIC output is shifted following a short cell | ||
|---|---|---|---|
| Product: | Base System | Reporter: | Jerry Mancini <mancini> |
| Component: | kern | Assignee: | Hartmut Brandt <harti> |
| Status: | Closed FIXED | ||
| Severity: | Affects Only Me | ||
| Priority: | Normal | ||
| Version: | 2.2.7-RELEASE | ||
| Hardware: | Any | ||
| OS: | Any | ||
Responsible Changed From-To: gnats-admin->freebsd-bugs Misfiled PR. Responsible Changed From-To: freebsd-bugs->mks Poul-Henning says that Mike is Mr. ATM. Responsible Changed From-To: mks->freebsd-bugs mks is no longer with us Responsible Changed From-To: freebsd-bugs->harti Assign to atm maintainer State Changed From-To: open->feedback Submitter asked whether the problem still exists and what ASIC he is refering to. State Changed From-To: feedback->closed This was a misfiled PR that does not relate to FreeBSD as Jerry told me. |
When the output port is configured for 53 or 54 byte mode, there is a problem in the output data following a short cell. For example, a cell with inserted ATM header of ef01ffff and a bltin of: 13886 13887 00104fa c601064e31c00422 bltin 0x42, 28, reg1, reg2, 0x1064e 13890 042 29a02fba 13891 042 97234f56 0015001 29a02fba 13892 042 5cbd4a33 0015002 97234f56 13893 042 6020de06 0015003 5cbd4a33 13894 042 d6b7394d 0015004 6020de06 13895 042 b953e015 0015005 d6b7394d 13896 042 03f79862 0015006 b953e015 13897 042 93b0f0f9 0015007 03f79862 13898 042 f9f272b0 0015008 93b0f0f9 13899 042 1a79271a 0015009 f9f272b0 13900 042 f31e73a9 001500a 1a79271a 13901 042 0000004e 001500b f31e73a9 13902 001500c 0000004e 13903 2 0001500d reg write is output as: 131698 0x00000000 139233 0xabcd0001 lastword 32 139419 0xeeef01ff 139652 0x2229a02f 139838 0xba97234f 140024 0x565cbd4a 140210 0x336020de 140396 0x06d6b739 140582 0x4db953e0 140768 0x1593b0f0 140954 0xf9f9f272 141140 0xb01a7927 141326 0x1af31e73 141512 0xa9000000 141698 0x4e000000 Notice that the header is shifted right by two bytes. Each word that follows is shifted right by 2 bytes. This example was run in 53-byte mode. How-To-Repeat: run atmout3_port.pl test with port cell size set to either 53 or 54 byte mode.