Bug 139743

Summary:

[ichsmb] [patch] ichsmb driver doesn't detects SMB bus on Asus P4B533/P4PE motherboards

Product:

Base System

Reporter:

Alexander <bas>

Component:

kern

Assignee:

Hiroki Sato <hrs>

Status:

In Progress ---

Severity:

Affects Only Me

CC:

hrs, takefu

Priority:

Normal

Version:

7.2-STABLE

Hardware:

Any

OS:

Any

Attachments:

Description	Flags
file.diff	none
sys_dev_pci_pci.c-RELENG_10_0.patch	none
sys_dev_pci_pci.c-RELENG_10_2.patch	none
sys_dev_pci_pci.c.diff RELENG_11_0	none
sys_dev_pci_pci.c.diff_RELENG_11_1	none
sys_dev_pci_pci.c.diff releng/11.2	none
sys_dev_pci_pci.c.diff_RELENG_12_0	none
sys_dev_pci_pci.c.diff_RELENG_13.0	none
sys_dev_pci_pci.c.diff_RELENG_13.1	none
sys_dev_pci_pci.c.diff_RELENG_13.2	none

Description Alexander 2009-10-19 06:00:10 UTC

Asus hides the SMBus PCI bridge within the ICH2 or ICH4 southbridge
on Asus P4B533/P4PE mainboards. So ichsmb driver doesn't detects
SMB bus.

Bug has been known as http://www.freebsd.org/cgi/query-pr.cgi?pr=60226 , but was closed by "feedback timeout".

Fix: I ported patch, given in http://www.freebsd.org/cgi/query-pr.cgi?pr=60226 to 7.2-STABLE. Ported patch goes in attach.

On my machine (Asus P4PE motherboard) SMBus works after patching.

Patch attached with submission follows:
How-To-Repeat: Include
device smbus
device ichsmb
device smb
to the kernel config file, recompile kernel and reboot.
New kernel will not detects SMB bus.
pciconf -lv will not list it too.

Comment 1 takefu 2011-02-08 10:08:43 UTC

Hi
It used it also with 8.2-RC3.

--- pci.c.patch begins here ---
--- sys/dev/pci/pci.c.orig	2010-12-22 02:09:25.000000000 +0900
+++ sys/dev/pci/pci.c	2011-02-08 16:16:27.000000000 +0900
@@ -111,6 +111,7 @@
 			    uint16_t data);
 static void		pci_enable_msix(device_t dev, u_int index,
 			    uint64_t address, uint32_t data);
+static void		pci_fix_asus_smbus(device_t dev);
 static void		pci_mask_msix(device_t dev, u_int index);
 static void		pci_unmask_msix(device_t dev, u_int index);
 static int		pci_msi_blacklisted(void);
@@ -188,47 +189,53 @@
 #define	PCI_QUIRK_MAP_REG	1 /* PCI map register in weird place */
 #define	PCI_QUIRK_DISABLE_MSI	2 /* MSI/MSI-X doesn't work */
 #define	PCI_QUIRK_ENABLE_MSI_VM	3 /* Older chipset in VM where MSI works */
+#define	PCI_QUIRK_FIXUP_ROUTINE 4 /* PCI needs a fix to continue */
 	int	arg1;
 	int	arg2;
+	void (*fixup_func)(device_t dev);
 };

 struct pci_quirk pci_quirks[] = {
 	/* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
-	{ 0x71138086, PCI_QUIRK_MAP_REG,	0x90,	 0 },
-	{ 0x719b8086, PCI_QUIRK_MAP_REG,	0x90,	 0 },
+	{ 0x71138086, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
+	{ 0x719b8086, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
 	/* As does the Serverworks OSB4 (the SMBus mapping register) */
-	{ 0x02001166, PCI_QUIRK_MAP_REG,	0x90,	 0 },
+	{ 0x02001166, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
+
+	/* The ASUS P4B-motherboards needs a hack to enable the Intel 801SMBus */
+	{ 0x24408086, PCI_QUIRK_FIXUP_ROUTINE,	0,	0, &pci_fix_asus_smbus },
+	{ 0x24C08086, PCI_QUIRK_FIXUP_ROUTINE,	0,	0, &pci_fix_asus_smbus },

 	/*
 	 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
 	 * or the CMIC-SL (AKA ServerWorks GC_LE).
 	 */
-	{ 0x00141166, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x00171166, PCI_QUIRK_DISABLE_MSI,	0,	0 },
+	{ 0x00141166, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x00171166, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

 	/*
 	 * MSI doesn't work on earlier Intel chipsets including
 	 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
 	 */
-	{ 0x25408086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x25508086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x25608086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x25708086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x25788086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x35808086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
+	{ 0x25408086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x25508086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x25608086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x25708086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x25788086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x35808086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

 	/*
 	 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
 	 * bridge.
 	 */
-	{ 0x74501022, PCI_QUIRK_DISABLE_MSI,	0,	0 },
+	{ 0x74501022, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

 	/*
 	 * Some virtualization environments emulate an older chipset
 	 * but support MSI just fine.  QEMU uses the Intel 82440.
 	 */
-	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM,	0,	0 },
+	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM,	0,	0, NULL },

 	{ 0 }
 };
@@ -435,6 +442,27 @@
 		cfg->hdrtype = 1;
 }

+/* asus p4b/p4pe hack */
+
+static void
+pci_fix_asus_smbus(device_t dev)
+{
+	int	pmccfg;
+
+	/* read subsystem vendor-id */
+	pmccfg = pci_read_config(dev, 0xF2, 2);
+	printf(" [-] pmccfg: %.4x\n",pmccfg);
+	if( pmccfg & 0x8 ){
+	    pmccfg &= ~0x8;
+	    pci_write_config(dev, 0xF2, pmccfg, 2);
+	    pmccfg = pci_read_config(dev, 0xF2, 2);
+	    if( pmccfg & 0x8 )
+		printf("Could not enable Intel 801SMBus!\n");
+	    else
+		printf("Enabled Intel 801SMBus\n");
+	}
+}
+
 /* extract header type specific config data */

 static void
@@ -2790,9 +2818,12 @@
 	 * Add additional, quirked resources.
 	 */
 	for (q = &pci_quirks[0]; q->devid; q++) {
-		if (q->devid == ((cfg->device << 16) | cfg->vendor)
-		    && q->type == PCI_QUIRK_MAP_REG)
-			pci_add_map(bus, dev, q->arg1, rl, force, 0);
+		if (q->devid == ((cfg->device << 16) | cfg->vendor) ){
+		    if( q->type == PCI_QUIRK_MAP_REG )
+			pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl, force, 0);
+		    else if( q->type == PCI_QUIRK_FIXUP_ROUTINE )
+			q->fixup_func(dev);
+		}
 	}

 	if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
--- pci.c.patch ends here ---

Comment 2 takefu 2011-02-08 10:12:30 UTC

Sorry!

Here is correct.


--- pci.c.patch begins here ---
--- sys/dev/pci/pci.c.orig	2010-12-22 02:09:25.000000000 +0900
+++ sys/dev/pci/pci.c	2011-02-08 19:06:23.000000000 +0900
@@ -111,6 +111,7 @@
 			    uint16_t data);
 static void		pci_enable_msix(device_t dev, u_int index,
 			    uint64_t address, uint32_t data);
+static void		pci_fix_asus_smbus(device_t dev);
 static void		pci_mask_msix(device_t dev, u_int index);
 static void		pci_unmask_msix(device_t dev, u_int index);
 static int		pci_msi_blacklisted(void);
@@ -188,47 +189,53 @@
 #define	PCI_QUIRK_MAP_REG	1 /* PCI map register in weird place */
 #define	PCI_QUIRK_DISABLE_MSI	2 /* MSI/MSI-X doesn't work */
 #define	PCI_QUIRK_ENABLE_MSI_VM	3 /* Older chipset in VM where MSI works */
+#define	PCI_QUIRK_FIXUP_ROUTINE 4 /* PCI needs a fix to continue */
 	int	arg1;
 	int	arg2;
+	void (*fixup_func)(device_t dev);
 };

 struct pci_quirk pci_quirks[] = {
 	/* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
-	{ 0x71138086, PCI_QUIRK_MAP_REG,	0x90,	 0 },
-	{ 0x719b8086, PCI_QUIRK_MAP_REG,	0x90,	 0 },
+	{ 0x71138086, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
+	{ 0x719b8086, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
 	/* As does the Serverworks OSB4 (the SMBus mapping register) */
-	{ 0x02001166, PCI_QUIRK_MAP_REG,	0x90,	 0 },
+	{ 0x02001166, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
+
+	/* The ASUS P4B-motherboards needs a hack to enable the Intel 801SMBus */
+	{ 0x24408086, PCI_QUIRK_FIXUP_ROUTINE,	0,	0, &pci_fix_asus_smbus },
+	{ 0x24C08086, PCI_QUIRK_FIXUP_ROUTINE,	0,	0, &pci_fix_asus_smbus },

 	/*
 	 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
 	 * or the CMIC-SL (AKA ServerWorks GC_LE).
 	 */
-	{ 0x00141166, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x00171166, PCI_QUIRK_DISABLE_MSI,	0,	0 },
+	{ 0x00141166, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x00171166, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

 	/*
 	 * MSI doesn't work on earlier Intel chipsets including
 	 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
 	 */
-	{ 0x25408086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x25508086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x25608086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x25708086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x25788086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x35808086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
+	{ 0x25408086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x25508086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x25608086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x25708086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x25788086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x35808086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

 	/*
 	 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
 	 * bridge.
 	 */
-	{ 0x74501022, PCI_QUIRK_DISABLE_MSI,	0,	0 },
+	{ 0x74501022, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

 	/*
 	 * Some virtualization environments emulate an older chipset
 	 * but support MSI just fine.  QEMU uses the Intel 82440.
 	 */
-	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM,	0,	0 },
+	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM,	0,	0, NULL },

 	{ 0 }
 };
@@ -435,6 +442,27 @@
 		cfg->hdrtype = 1;
 }

+/* asus p4b/p4pe hack */
+
+static void
+pci_fix_asus_smbus(device_t dev)
+{
+	int	pmccfg;
+
+	/* read subsystem vendor-id */
+	pmccfg = pci_read_config(dev, 0xF2, 2);
+	printf(" [-] pmccfg: %.4x\n",pmccfg);
+	if( pmccfg & 0x8 ){
+	    pmccfg &= ~0x8;
+	    pci_write_config(dev, 0xF2, pmccfg, 2);
+	    pmccfg = pci_read_config(dev, 0xF2, 2);
+	    if( pmccfg & 0x8 )
+		printf("Could not enable Intel 801SMBus!\n");
+	    else
+		printf("Enabled Intel 801SMBus\n");
+	}
+}
+
 /* extract header type specific config data */

 static void
@@ -2790,9 +2818,12 @@
 	 * Add additional, quirked resources.
 	 */
 	for (q = &pci_quirks[0]; q->devid; q++) {
-		if (q->devid == ((cfg->device << 16) | cfg->vendor)
-		    && q->type == PCI_QUIRK_MAP_REG)
+		if (q->devid == ((cfg->device << 16) | cfg->vendor) ){
+		    if( q->type == PCI_QUIRK_MAP_REG )
 			pci_add_map(bus, dev, q->arg1, rl, force, 0);
+		    else if( q->type == PCI_QUIRK_FIXUP_ROUTINE )
+			q->fixup_func(dev);
+		}
 	}

 	if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
--- pci.c.patch ends here ---

Comment 3 takefu 2011-11-22 02:44:08 UTC

Corresponds to RELENG_9 :-)

--- pci.c.patch begins here ---
--- sys/dev/pci/pci.c.orig	2011-11-17 18:19:12.000000000 +0900
+++ sys/dev/pci/pci.c	2011-11-17 18:28:57.000000000 +0900
@@ -112,6 +112,7 @@
 			    uint16_t data);
 static void		pci_enable_msix(device_t dev, u_int index,
 			    uint64_t address, uint32_t data);
+static void		pci_fix_asus_smbus(device_t dev);
 static void		pci_mask_msix(device_t dev, u_int index);
 static void		pci_unmask_msix(device_t dev, u_int index);
 static int		pci_msi_blacklisted(void);
@@ -190,47 +191,52 @@
 #define	PCI_QUIRK_MAP_REG	1 /* PCI map register in weird place */
 #define	PCI_QUIRK_DISABLE_MSI	2 /* MSI/MSI-X doesn't work */
 #define	PCI_QUIRK_ENABLE_MSI_VM	3 /* Older chipset in VM where MSI works */
+#define	PCI_QUIRK_FIXUP_ROUTINE 4 /* PCI needs a fix to continue */
 	int	arg1;
 	int	arg2;
+	void (*fixup_func)(device_t dev);
 };

 struct pci_quirk pci_quirks[] = {
 	/* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
-	{ 0x71138086, PCI_QUIRK_MAP_REG,	0x90,	 0 },
-	{ 0x719b8086, PCI_QUIRK_MAP_REG,	0x90,	 0 },
+	{ 0x71138086, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
+	{ 0x719b8086, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
 	/* As does the Serverworks OSB4 (the SMBus mapping register) */
-	{ 0x02001166, PCI_QUIRK_MAP_REG,	0x90,	 0 },
+	{ 0x02001166, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
+	/* The ASUS P4B-motherboards needs a hack to enable the Intel 801SMBus */
+	{ 0x24408086, PCI_QUIRK_FIXUP_ROUTINE,	0,	0, &pci_fix_asus_smbus },
+	{ 0x24C08086, PCI_QUIRK_FIXUP_ROUTINE,	0,	0, &pci_fix_asus_smbus },

 	/*
 	 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
 	 * or the CMIC-SL (AKA ServerWorks GC_LE).
 	 */
-	{ 0x00141166, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x00171166, PCI_QUIRK_DISABLE_MSI,	0,	0 },
+	{ 0x00141166, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x00171166, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

 	/*
 	 * MSI doesn't work on earlier Intel chipsets including
 	 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
 	 */
-	{ 0x25408086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x25508086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x25608086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x25708086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x25788086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x35808086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
+	{ 0x25408086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x25508086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x25608086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x25708086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x25788086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x35808086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

 	/*
 	 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
 	 * bridge.
 	 */
-	{ 0x74501022, PCI_QUIRK_DISABLE_MSI,	0,	0 },
+	{ 0x74501022, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

 	/*
 	 * Some virtualization environments emulate an older chipset
 	 * but support MSI just fine.  QEMU uses the Intel 82440.
 	 */
-	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM,	0,	0 },
+	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM,	0,	0, NULL },

 	{ 0 }
 };
@@ -485,6 +491,26 @@
 	if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
 		cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
 }
+/* asus p4b/p4pe hack */
+
+static void
+pci_fix_asus_smbus(device_t dev)
+{
+	int	pmccfg;
+
+	/* read subsystem vendor-id */
+	pmccfg = pci_read_config(dev, 0xF2, 2);
+	printf(" [-] pmccfg: %.4x\n",pmccfg);
+	if( pmccfg & 0x8 ){
+		pmccfg &= ~0x8;
+		pci_write_config(dev, 0xF2, pmccfg, 2);
+		pmccfg = pci_read_config(dev, 0xF2, 2);
+		if( pmccfg & 0x8 )
+			printf("Could not enable Intel 801SMBus!\n");
+		else
+			printf("Enabled Intel 801SMBus\n");
+	}
+}

 /* extract header type specific config data */

@@ -3044,9 +3070,12 @@
 	 * Add additional, quirked resources.
 	 */
 	for (q = &pci_quirks[0]; q->devid; q++) {
-		if (q->devid == ((cfg->device << 16) | cfg->vendor)
-		    && q->type == PCI_QUIRK_MAP_REG)
+		if (q->devid == ((cfg->device << 16) | cfg->vendor) ){
+		    if( q->type == PCI_QUIRK_MAP_REG )
 			pci_add_map(bus, dev, q->arg1, rl, force, 0);
+		    else if( q->type == PCI_QUIRK_FIXUP_ROUTINE )
+			q->fixup_func(dev);
+		}
 	}

 	if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {

--- pci.c.patch ends here ---

Comment 4 takefu 2013-02-12 10:06:25 UTC

quick hack RELENG_9_1

I think that it is a patch that looks alike.
PR#kern/70810

Old PR is thrown away, and it wishes the adoption of new PR.
PR#i386/139743


--- pci.c.patch begins here ---
--- sys/dev/pci/pci.c.orig	2012-11-17 17:47:51.000000000 +0900
+++ sys/dev/pci/pci.c	2013-02-12 17:24:51.000000000 +0900
@@ -134,6 +134,7 @@
 static void		pci_resume_msix(device_t dev);
 static int		pci_remap_intr_method(device_t bus, device_t dev,
 			    u_int irq);
+static void		pci_fix_asus_smbus(device_t dev);

 static device_method_t pci_methods[] = {
 	/* Device interface */
@@ -206,53 +207,55 @@
 #define	PCI_QUIRK_DISABLE_MSI	2 /* MSI/MSI-X doesn't work */
 #define	PCI_QUIRK_ENABLE_MSI_VM	3 /* Older chipset in VM where MSI works */
 #define	PCI_QUIRK_UNMAP_REG	4 /* Ignore PCI map register */
+#define	PCI_QUIRK_FIXUP_ROUTINE	5 /* PCI needs a fix to continue */
 	int	arg1;
 	int	arg2;
+void (*fixup_func)(device_t dev);
 };

 static const struct pci_quirk const pci_quirks[] = {
 	/* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
-	{ 0x71138086, PCI_QUIRK_MAP_REG,	0x90,	 0 },
-	{ 0x719b8086, PCI_QUIRK_MAP_REG,	0x90,	 0 },
+	{ 0x71138086, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
+	{ 0x719b8086, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
 	/* As does the Serverworks OSB4 (the SMBus mapping register) */
-	{ 0x02001166, PCI_QUIRK_MAP_REG,	0x90,	 0 },
+	{ 0x02001166, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },

 	/*
 	 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
 	 * or the CMIC-SL (AKA ServerWorks GC_LE).
 	 */
-	{ 0x00141166, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x00171166, PCI_QUIRK_DISABLE_MSI,	0,	0 },
+	{ 0x00141166, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x00171166, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

 	/*
 	 * MSI doesn't work on earlier Intel chipsets including
 	 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
 	 */
-	{ 0x25408086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x25508086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x25608086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x25708086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x25788086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
-	{ 0x35808086, PCI_QUIRK_DISABLE_MSI,	0,	0 },
+	{ 0x25408086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x25508086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x25608086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x25708086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x25788086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
+	{ 0x35808086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

 	/*
 	 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
 	 * bridge.
 	 */
-	{ 0x74501022, PCI_QUIRK_DISABLE_MSI,	0,	0 },
+	{ 0x74501022, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

 	/*
 	 * MSI-X doesn't work with at least LSI SAS1068E passed through by
 	 * VMware.
 	 */
-	{ 0x079015ad, PCI_QUIRK_DISABLE_MSI,	0,	0 },
+	{ 0x079015ad, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

 	/*
 	 * Some virtualization environments emulate an older chipset
 	 * but support MSI just fine.  QEMU uses the Intel 82440.
 	 */
-	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM,	0,	0 },
+	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM,	0,	0, NULL },

 	/*
 	 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus
@@ -262,7 +265,16 @@
 	 * For SB600 A21 and later, firmware must set the bit to hide it.
 	 * For SB700 and later, it is unused and hardcoded to zero.
 	 */
-	{ 0x43851002, PCI_QUIRK_UNMAP_REG,	0x14,	0 },
+	{ 0x43851002, PCI_QUIRK_UNMAP_REG,	0x14,	0, NULL },
+
+	/*
+	 * kern/70810: [pci] [patch] Enable SMBus device on Asus P4B series motherboards
+	{ 0x24408086, PCI_QUIRK_CLEAR_BITS,	0xf2,	0x0108, NULL },
+	 * i386/139743: [ichsmb] [patch] ichsmb driver doesn't detects SMB bus on Asus P4B533/P4PE motherboards
+	 */
+	/* The ASUS P4B-motherboards needs a hack to enable the Intel 801SMBus */
+	{ 0x24408086, PCI_QUIRK_FIXUP_ROUTINE,	0,	0, &pci_fix_asus_smbus },
+	{ 0x24C08086, PCI_QUIRK_FIXUP_ROUTINE,	0,	0, &pci_fix_asus_smbus },

 	{ 0 }
 };
@@ -518,6 +530,27 @@
 		cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
 }

+/* asus p4b/p4pe hack */
+
+static void
+pci_fix_asus_smbus(device_t dev)
+{
+	int	pmccfg;
+
+	/* read subsystem vendor-id */
+	pmccfg = pci_read_config(dev, 0xF2, 2);
+	printf(" [-] pmccfg: %.4x\n",pmccfg);
+	if( pmccfg & 0x8 ){
+		pmccfg &= ~0x8;
+		pci_write_config(dev, 0xF2, pmccfg, 2);
+		pmccfg = pci_read_config(dev, 0xF2, 2);
+		if( pmccfg & 0x8 )
+			printf("Could not enable Intel 801SMBus!\n");
+		else
+			printf("Enabled Intel 801SMBus\n");
+	}
+}
+
 /* extract header type specific config data */

 static void
@@ -3091,8 +3124,12 @@
 	 * Add additional, quirked resources.
 	 */
 	for (q = &pci_quirks[0]; q->devid != 0; q++)
-		if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG)
+		if (q->devid == ((cfg->device << 16) | cfg->vendor) ){
+		    if( q->type == PCI_QUIRK_MAP_REG )
 			pci_add_map(bus, dev, q->arg1, rl, force, 0);
+		    else if( q->type == PCI_QUIRK_FIXUP_ROUTINE )
+			q->fixup_func(dev);
+		}

 	if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
 #ifdef __PCI_REROUTE_INTERRUPT
--- pci.c.patch ends here ---

Comment 5 Remko Lodder freebsd_committer

2013-02-13 06:28:46 UTC

Responsible Changed
From-To: freebsd-i386->freebsd-bugs

Reassign to -bugs, this isn't i386 specific.

Comment 6 takefu 2014-07-09 23:36:32 UTC

Created attachment 144548 [details]
sys_dev_pci_pci.c-RELENG_10_0.patch

10.0-RELEASE

(In reply to Remko Lodder from comment #5)
> Responsible Changed
> From-To: freebsd-i386->freebsd-bugs
> 
> Reassign to -bugs, this isn't i386 specific.

Comment 7 takefu 2015-09-30 06:25:20 UTC

Created attachment 161560 [details]
sys_dev_pci_pci.c-RELENG_10_2.patch

RELEASE 10.2

Comment 8 takefu 2016-10-24 22:47:39 UTC

Created attachment 176126 [details]
sys_dev_pci_pci.c.diff RELENG_11_0

Comment 9 takefu 2017-08-02 22:41:03 UTC

Created attachment 184971 [details]
sys_dev_pci_pci.c.diff_RELENG_11_1

Comment 10 takefu 2018-05-01 05:48:07 UTC

(In reply to takefu from comment #9)

Applying the patch correctly starts recognizing it as SMBus device.
When starting with kernel after patch, you need to load ichsmb module.

/boot/loader.conf
ichsmb_load="YES"
smb_load="YES"

Comment 11 takefu 2018-07-09 04:09:11 UTC

Created attachment 194974 [details]
sys_dev_pci_pci.c.diff releng/11.2

Merge to releng/11.2

Comment 12 takefu 2019-01-28 07:19:52 UTC

Created attachment 201473 [details]
sys_dev_pci_pci.c.diff_RELENG_12_0

sys_dev_pci_pci.c.diff releng/12.0

Merge to releng/12.0

Comment 13 takefu 2021-08-27 05:11:01 UTC

Created attachment 227466 [details]
sys_dev_pci_pci.c.diff_RELENG_13.0

Comment 14 takefu 2022-07-19 05:12:23 UTC

Created attachment 235345 [details]
sys_dev_pci_pci.c.diff_RELENG_13.1

Comment 15 takefu 2023-05-06 18:43:58 UTC

Created attachment 242021 [details]
sys_dev_pci_pci.c.diff_RELENG_13.2

RELENG_13.2