Bug 165951

Description Adrian Chadd 2012-03-11 22:20:09 UTC

The AR913x WMAC sits off the Atheros Host Bus (AHB), along with the usb, gmac, etc. The APB (peripheral bus) contains the UART, etc and is a part of the AHB.

Trouble is, the AHB code in -HEAD includes the USB because the USB IRQ sits inside the APB MISC interrupt status word. The other peripherals (GMAC0, GMAC1, WMAC/PCI, etc) are primary MIPS IRQs.

So the AHB devices (besides USB) sit off the nexus, rather than off the AHB. There's no AHB glue, per se, and thus there's no convenient place to put the WMAC DDR flush. For the AR713x/AR71xx there's a PCIe/PCI bus nexus and the IP2 flush is done there.

Fix: 

I'm not sure yet. I think the right thing to do is:

* create the AHB bus;
* have the IRQ handling done inside AHB - mapping the MISC interrupts to say IRQ 15 - 31;
* Create APB;
* Have the APB peripherals now use the MISC interrupts that are between AHB IRQs 15->31;
* Have USB also use the relevant MISC interrupt that's between 15 and 31;
* The APB interrupt code would just punt to the AHB.