Bug 222634
| Summary: | ffec: Support i.MX7D and performance improvements | ||||||||||||||||
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| Product: | Base System | Reporter: | sebastian.huber | ||||||||||||||
| Component: | arm | Assignee: | Ian Lepore <ian> | ||||||||||||||
| Status: | Closed FIXED | ||||||||||||||||
| Severity: | Affects Some People | CC: | emaste, ian | ||||||||||||||
| Priority: | --- | ||||||||||||||||
| Version: | CURRENT | ||||||||||||||||
| Hardware: | arm | ||||||||||||||||
| OS: | Any | ||||||||||||||||
| Attachments: |
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Description
sebastian.huber
2017-09-27 06:45:09 UTC
Created attachment 186752 [details]
fec: Increase descriptor ring alignment
Created attachment 186753 [details]
ffec: Add FECFLAG_AVB variant flag
Created attachment 186754 [details]
ffec: Avoid AXI bus issues due to a MAC reset
Created attachment 186755 [details]
ffec: Support up to three interrupt requests
Thanks, this all sounds like great stuff. It's going to take me a few days to look at it, but I wanted to get a reply in right away to let you know I'm on it. Created attachment 186905 [details]
ffec: Use RACC[SHIFT16]
Created attachment 186906 [details]
ffec: Use RACC[SHIFT16]
A commit references this bug: Author: ian Date: Sat Oct 28 16:50:24 UTC 2017 New revision: 325054 URL: https://svnweb.freebsd.org/changeset/base/325054 Log: Increase the alignment of the rx/tx descriptor ring buffers to 64 bytes. 16 was the correct alignment for older hardware, but the imx7 requires 64-byte alignment, which is a fine value to use on all systems. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de Changes: head/sys/dev/ffec/if_ffecreg.h A commit references this bug: Author: ian Date: Sat Oct 28 17:06:14 UTC 2017 New revision: 325055 URL: https://svnweb.freebsd.org/changeset/base/325055 Log: Add FECFLAG_AVB variant flag to support new features on imx7. This flag is analogous to the Linux driver FEC_QUIRK_HAS_AVB. It indicates an FEC with support for Audio Video Bridging (AVB). This indicator is used for various other parts in the Linux driver (drivers/net/ethernet/freescale/fec_main.c). Use it to customize the receive/transmit buffer alignment. The receive buffer alignment increased to 64-bytes on the i.MX 6SoloX and i.MX 7Dual. There are no hard alignment restrictions for transmit buffers on these chips. Fix the ffec_softc::fectype type to provide enough storage for the feature flags. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de Changes: head/sys/dev/ffec/if_ffec.c head/sys/dev/ffec/if_ffecreg.h A commit references this bug: Author: ian Date: Sat Oct 28 17:30:49 UTC 2017 New revision: 325056 URL: https://svnweb.freebsd.org/changeset/base/325056 Log: Avoid AXI bus issues due to a MAC reset on imx6sx and imx7. When the FEC is connected to the AXI bus (indicated by AVB flag), a MAC reset while a bus transaction is pending can hang the bus. Instead of resetting, turn off the ENABLE bit, which allows the hardware to complete any in-progress transfers (appending a bad CRC to any partial packet) and release the AXI bus. This could probably be done unconditionally for all hardware variants, but that hasn't been tested. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de Changes: head/sys/dev/ffec/if_ffec.c A commit references this bug: Author: ian Date: Sat Oct 28 19:08:06 UTC 2017 New revision: 325061 URL: https://svnweb.freebsd.org/changeset/base/325061 Log: Support up to 3 IRQs in the ffec driver. Newer hardware splits the interrupts onto 3 different irq lines, but the docs barely mention that there are multiple interrupts, and do not detail how they're split up. The code now supports 1-3 irqs, and uses the same interrupt service routine to handle all of them. I modified the submitted changes to use bus_alloc_resources() instead of using loops to allocate each irq separately. Thus, blame any bugs on me (I can't actually test on imx7 hardware). PR: 222634 Submitted by: sebastian.huber@embedded-brains.de Changes: head/sys/dev/ffec/if_ffec.c A commit references this bug: Author: ian Date: Sat Oct 28 19:34:08 UTC 2017 New revision: 325063 URL: https://svnweb.freebsd.org/changeset/base/325063 Log: Use the 16-bit receive shift feature in ffec hardware that supports it. When available, enabling this feature causes the hardware to write data to the receive buffer starting at a 16-bit offset from the start address. This eliminates the need to copy the data after receiving to re-align the protocol headers to a 32-bit boundary. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de Changes: head/sys/dev/ffec/if_ffec.c I finally got around to committing all these patches, thank you for submitting them. I made some small changes along the way, mostly to comments, and to the way multiple irq resources are allocated. I'm also going to split the fectype field of the softc into separate type and flags, because there is already one bug in the code where I've used == and forgoten to mask off the flag bits. I didn't set MFC reminders in the commits, but I am going to MFC all this to 11-stable after some testing; I'll close the PR after that's done. Thanks, for the integration. I implemented some other things two weeks ago: https://git.rtems.org/rtems-libbsd/commit/?id=0cb40755cc3e20ebfccf427d6061920963d48b8e https://git.rtems.org/rtems-libbsd/commit/?id=0323c286e32934979043d14d69660db4ba4c3181 https://git.rtems.org/rtems-libbsd/commit/?id=a8a9cf1847f2832e9e5ce54e862063d7907fc42d I have to rebase the work and generate patches for FreeBSD. I am not sure what is the best way to integrate the checksum offload (enhanced descriptors). The DMA buffer synchronization differs between various drivers. This makes it difficult for me to pick up the right ones. A commit references this bug: Author: ian Date: Sat Jan 6 21:19:53 UTC 2018 New revision: 327638 URL: https://svnweb.freebsd.org/changeset/base/327638 Log: MFC r325045, r325054-r325056, r325061, r325063, r325065 r325045: Actually release resources in detach() rather than just returning EBUSY. This will enable use of 'devctl disable', allow creation of a module, etc. r325054: Increase the alignment of the rx/tx descriptor ring buffers to 64 bytes. 16 was the correct alignment for older hardware, but the imx7 requires 64-byte alignment, which is a fine value to use on all systems. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325055: Add FECFLAG_AVB variant flag to support new features on imx7. This flag is analogous to the Linux driver FEC_QUIRK_HAS_AVB. It indicates an FEC with support for Audio Video Bridging (AVB). This indicator is used for various other parts in the Linux driver (drivers/net/ethernet/freescale/fec_main.c). Use it to customize the receive/transmit buffer alignment. The receive buffer alignment increased to 64-bytes on the i.MX 6SoloX and i.MX 7Dual. There are no hard alignment restrictions for transmit buffers on these chips. Fix the ffec_softc::fectype type to provide enough storage for the feature flags. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325056: Avoid AXI bus issues due to a MAC reset on imx6sx and imx7. When the FEC is connected to the AXI bus (indicated by AVB flag), a MAC reset while a bus transaction is pending can hang the bus. Instead of resetting, turn off the ENABLE bit, which allows the hardware to complete any in-progress transfers (appending a bad CRC to any partial packet) and release the AXI bus. This could probably be done unconditionally for all hardware variants, but that hasn't been tested. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325061: Support up to 3 IRQs in the ffec driver. Newer hardware splits the interrupts onto 3 different irq lines, but the docs barely mention that there are multiple interrupts, and do not detail how they're split up. The code now supports 1-3 irqs, and uses the same interrupt service routine to handle all of them. I modified the submitted changes to use bus_alloc_resources() instead of using loops to allocate each irq separately. Thus, blame any bugs on me (I can't actually test on imx7 hardware). PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325063: Use the 16-bit receive shift feature in ffec hardware that supports it. When available, enabling this feature causes the hardware to write data to the receive buffer starting at a 16-bit offset from the start address. This eliminates the need to copy the data after receiving to re-align the protocol headers to a 32-bit boundary. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325065: Split the hardware type enum and the hw feature flags bits into separate fields in the softc; they're ORed together in the ofw_compat_data. I already caught myself doing 'sc->fectype == <enum val>' without masking out the feature bits in one place, and that's sure to happen again. Glomming them together is convenient for storing them in the ofw_compat_data array, but there's no reason to keep them together in the softc. Changes: _U stable/11/ stable/11/sys/dev/ffec/if_ffec.c stable/11/sys/dev/ffec/if_ffecreg.h stable/11/sys/dev/sdhci/fsl_sdhci.c A commit references this bug: Author: ian Date: Sat Jan 6 21:19:53 UTC 2018 New revision: 327638 URL: https://svnweb.freebsd.org/changeset/base/327638 Log: MFC r325045, r325054-r325056, r325061, r325063, r325065 r325045: Actually release resources in detach() rather than just returning EBUSY. This will enable use of 'devctl disable', allow creation of a module, etc. r325054: Increase the alignment of the rx/tx descriptor ring buffers to 64 bytes. 16 was the correct alignment for older hardware, but the imx7 requires 64-byte alignment, which is a fine value to use on all systems. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325055: Add FECFLAG_AVB variant flag to support new features on imx7. This flag is analogous to the Linux driver FEC_QUIRK_HAS_AVB. It indicates an FEC with support for Audio Video Bridging (AVB). This indicator is used for various other parts in the Linux driver (drivers/net/ethernet/freescale/fec_main.c). Use it to customize the receive/transmit buffer alignment. The receive buffer alignment increased to 64-bytes on the i.MX 6SoloX and i.MX 7Dual. There are no hard alignment restrictions for transmit buffers on these chips. Fix the ffec_softc::fectype type to provide enough storage for the feature flags. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325056: Avoid AXI bus issues due to a MAC reset on imx6sx and imx7. When the FEC is connected to the AXI bus (indicated by AVB flag), a MAC reset while a bus transaction is pending can hang the bus. Instead of resetting, turn off the ENABLE bit, which allows the hardware to complete any in-progress transfers (appending a bad CRC to any partial packet) and release the AXI bus. This could probably be done unconditionally for all hardware variants, but that hasn't been tested. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325061: Support up to 3 IRQs in the ffec driver. Newer hardware splits the interrupts onto 3 different irq lines, but the docs barely mention that there are multiple interrupts, and do not detail how they're split up. The code now supports 1-3 irqs, and uses the same interrupt service routine to handle all of them. I modified the submitted changes to use bus_alloc_resources() instead of using loops to allocate each irq separately. Thus, blame any bugs on me (I can't actually test on imx7 hardware). PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325063: Use the 16-bit receive shift feature in ffec hardware that supports it. When available, enabling this feature causes the hardware to write data to the receive buffer starting at a 16-bit offset from the start address. This eliminates the need to copy the data after receiving to re-align the protocol headers to a 32-bit boundary. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325065: Split the hardware type enum and the hw feature flags bits into separate fields in the softc; they're ORed together in the ofw_compat_data. I already caught myself doing 'sc->fectype == <enum val>' without masking out the feature bits in one place, and that's sure to happen again. Glomming them together is convenient for storing them in the ofw_compat_data array, but there's no reason to keep them together in the softc. Changes: _U stable/11/ stable/11/sys/dev/ffec/if_ffec.c stable/11/sys/dev/ffec/if_ffecreg.h stable/11/sys/dev/sdhci/fsl_sdhci.c A commit references this bug: Author: ian Date: Sat Jan 6 21:19:53 UTC 2018 New revision: 327638 URL: https://svnweb.freebsd.org/changeset/base/327638 Log: MFC r325045, r325054-r325056, r325061, r325063, r325065 r325045: Actually release resources in detach() rather than just returning EBUSY. This will enable use of 'devctl disable', allow creation of a module, etc. r325054: Increase the alignment of the rx/tx descriptor ring buffers to 64 bytes. 16 was the correct alignment for older hardware, but the imx7 requires 64-byte alignment, which is a fine value to use on all systems. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325055: Add FECFLAG_AVB variant flag to support new features on imx7. This flag is analogous to the Linux driver FEC_QUIRK_HAS_AVB. It indicates an FEC with support for Audio Video Bridging (AVB). This indicator is used for various other parts in the Linux driver (drivers/net/ethernet/freescale/fec_main.c). Use it to customize the receive/transmit buffer alignment. The receive buffer alignment increased to 64-bytes on the i.MX 6SoloX and i.MX 7Dual. There are no hard alignment restrictions for transmit buffers on these chips. Fix the ffec_softc::fectype type to provide enough storage for the feature flags. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325056: Avoid AXI bus issues due to a MAC reset on imx6sx and imx7. When the FEC is connected to the AXI bus (indicated by AVB flag), a MAC reset while a bus transaction is pending can hang the bus. Instead of resetting, turn off the ENABLE bit, which allows the hardware to complete any in-progress transfers (appending a bad CRC to any partial packet) and release the AXI bus. This could probably be done unconditionally for all hardware variants, but that hasn't been tested. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325061: Support up to 3 IRQs in the ffec driver. Newer hardware splits the interrupts onto 3 different irq lines, but the docs barely mention that there are multiple interrupts, and do not detail how they're split up. The code now supports 1-3 irqs, and uses the same interrupt service routine to handle all of them. I modified the submitted changes to use bus_alloc_resources() instead of using loops to allocate each irq separately. Thus, blame any bugs on me (I can't actually test on imx7 hardware). PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325063: Use the 16-bit receive shift feature in ffec hardware that supports it. When available, enabling this feature causes the hardware to write data to the receive buffer starting at a 16-bit offset from the start address. This eliminates the need to copy the data after receiving to re-align the protocol headers to a 32-bit boundary. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325065: Split the hardware type enum and the hw feature flags bits into separate fields in the softc; they're ORed together in the ofw_compat_data. I already caught myself doing 'sc->fectype == <enum val>' without masking out the feature bits in one place, and that's sure to happen again. Glomming them together is convenient for storing them in the ofw_compat_data array, but there's no reason to keep them together in the softc. Changes: _U stable/11/ stable/11/sys/dev/ffec/if_ffec.c stable/11/sys/dev/ffec/if_ffecreg.h stable/11/sys/dev/sdhci/fsl_sdhci.c A commit references this bug: Author: ian Date: Sat Jan 6 21:19:53 UTC 2018 New revision: 327638 URL: https://svnweb.freebsd.org/changeset/base/327638 Log: MFC r325045, r325054-r325056, r325061, r325063, r325065 r325045: Actually release resources in detach() rather than just returning EBUSY. This will enable use of 'devctl disable', allow creation of a module, etc. r325054: Increase the alignment of the rx/tx descriptor ring buffers to 64 bytes. 16 was the correct alignment for older hardware, but the imx7 requires 64-byte alignment, which is a fine value to use on all systems. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325055: Add FECFLAG_AVB variant flag to support new features on imx7. This flag is analogous to the Linux driver FEC_QUIRK_HAS_AVB. It indicates an FEC with support for Audio Video Bridging (AVB). This indicator is used for various other parts in the Linux driver (drivers/net/ethernet/freescale/fec_main.c). Use it to customize the receive/transmit buffer alignment. The receive buffer alignment increased to 64-bytes on the i.MX 6SoloX and i.MX 7Dual. There are no hard alignment restrictions for transmit buffers on these chips. Fix the ffec_softc::fectype type to provide enough storage for the feature flags. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325056: Avoid AXI bus issues due to a MAC reset on imx6sx and imx7. When the FEC is connected to the AXI bus (indicated by AVB flag), a MAC reset while a bus transaction is pending can hang the bus. Instead of resetting, turn off the ENABLE bit, which allows the hardware to complete any in-progress transfers (appending a bad CRC to any partial packet) and release the AXI bus. This could probably be done unconditionally for all hardware variants, but that hasn't been tested. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325061: Support up to 3 IRQs in the ffec driver. Newer hardware splits the interrupts onto 3 different irq lines, but the docs barely mention that there are multiple interrupts, and do not detail how they're split up. The code now supports 1-3 irqs, and uses the same interrupt service routine to handle all of them. I modified the submitted changes to use bus_alloc_resources() instead of using loops to allocate each irq separately. Thus, blame any bugs on me (I can't actually test on imx7 hardware). PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325063: Use the 16-bit receive shift feature in ffec hardware that supports it. When available, enabling this feature causes the hardware to write data to the receive buffer starting at a 16-bit offset from the start address. This eliminates the need to copy the data after receiving to re-align the protocol headers to a 32-bit boundary. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325065: Split the hardware type enum and the hw feature flags bits into separate fields in the softc; they're ORed together in the ofw_compat_data. I already caught myself doing 'sc->fectype == <enum val>' without masking out the feature bits in one place, and that's sure to happen again. Glomming them together is convenient for storing them in the ofw_compat_data array, but there's no reason to keep them together in the softc. Changes: _U stable/11/ stable/11/sys/dev/ffec/if_ffec.c stable/11/sys/dev/ffec/if_ffecreg.h stable/11/sys/dev/sdhci/fsl_sdhci.c A commit references this bug: Author: ian Date: Sat Jan 6 21:19:53 UTC 2018 New revision: 327638 URL: https://svnweb.freebsd.org/changeset/base/327638 Log: MFC r325045, r325054-r325056, r325061, r325063, r325065 r325045: Actually release resources in detach() rather than just returning EBUSY. This will enable use of 'devctl disable', allow creation of a module, etc. r325054: Increase the alignment of the rx/tx descriptor ring buffers to 64 bytes. 16 was the correct alignment for older hardware, but the imx7 requires 64-byte alignment, which is a fine value to use on all systems. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325055: Add FECFLAG_AVB variant flag to support new features on imx7. This flag is analogous to the Linux driver FEC_QUIRK_HAS_AVB. It indicates an FEC with support for Audio Video Bridging (AVB). This indicator is used for various other parts in the Linux driver (drivers/net/ethernet/freescale/fec_main.c). Use it to customize the receive/transmit buffer alignment. The receive buffer alignment increased to 64-bytes on the i.MX 6SoloX and i.MX 7Dual. There are no hard alignment restrictions for transmit buffers on these chips. Fix the ffec_softc::fectype type to provide enough storage for the feature flags. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325056: Avoid AXI bus issues due to a MAC reset on imx6sx and imx7. When the FEC is connected to the AXI bus (indicated by AVB flag), a MAC reset while a bus transaction is pending can hang the bus. Instead of resetting, turn off the ENABLE bit, which allows the hardware to complete any in-progress transfers (appending a bad CRC to any partial packet) and release the AXI bus. This could probably be done unconditionally for all hardware variants, but that hasn't been tested. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325061: Support up to 3 IRQs in the ffec driver. Newer hardware splits the interrupts onto 3 different irq lines, but the docs barely mention that there are multiple interrupts, and do not detail how they're split up. The code now supports 1-3 irqs, and uses the same interrupt service routine to handle all of them. I modified the submitted changes to use bus_alloc_resources() instead of using loops to allocate each irq separately. Thus, blame any bugs on me (I can't actually test on imx7 hardware). PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325063: Use the 16-bit receive shift feature in ffec hardware that supports it. When available, enabling this feature causes the hardware to write data to the receive buffer starting at a 16-bit offset from the start address. This eliminates the need to copy the data after receiving to re-align the protocol headers to a 32-bit boundary. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325065: Split the hardware type enum and the hw feature flags bits into separate fields in the softc; they're ORed together in the ofw_compat_data. I already caught myself doing 'sc->fectype == <enum val>' without masking out the feature bits in one place, and that's sure to happen again. Glomming them together is convenient for storing them in the ofw_compat_data array, but there's no reason to keep them together in the softc. Changes: _U stable/11/ stable/11/sys/dev/ffec/if_ffec.c stable/11/sys/dev/ffec/if_ffecreg.h stable/11/sys/dev/sdhci/fsl_sdhci.c All these patches have been committed and mfc'd to 11-stable. For further patches, please open a new PR, or open a Phabriacator review for them at https://reviews.freebsd.org/ |
