Bug 227591

Summary: [NEW PORT] devel/yosys - Verilog RTL syntensis
Product: Ports & Packages Reporter: Johnny Sorocil <jsorocil>
Component: Individual Port(s)Assignee: Tobias Kortkamp <tobik>
Status: Closed FIXED    
Severity: Affects Only Me    
Priority: ---    
Version: Latest   
Hardware: Any   
OS: Any   
Attachments:
Description Flags
svn diff of the port none

Description Johnny Sorocil 2018-04-17 21:00:52 UTC 
Created attachment 192600 [details]
svn diff of the port

Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.

WWW: http://www.clifford.at/yosys/

portlint: looks fine
poudriere testport: ok
Comment 1 Tobias Kortkamp freebsd_committer freebsd_triage 2018-05-16 08:17:43 UTC 
See https://forums.freebsd.org/threads/new-ports-lattice-fpga-tools.65552/ for
some feedback.
Comment 2 commit-hook freebsd_committer freebsd_triage 2018-06-06 14:19:58 UTC 
A commit references this bug:

Author: tobik
Date: Wed Jun  6 14:19:52 UTC 2018
New revision: 471844
URL: https://svnweb.freebsd.org/changeset/ports/471844

Log:
  New port: devel/yosys

  Yosys is a framework for Verilog RTL synthesis.  It currently has
  extensive Verilog-2005 support and provides a basic set of synthesis
  algorithms for various application domains.

  WWW: http://www.clifford.at/yosys/

  PR:		227591
  Submitted by:	Johnny Sorocil <jsorocil@gmail.com>
  Differential Revision:	https://reviews.freebsd.org/D15632

Changes:
  head/devel/Makefile
  head/devel/yosys/
  head/devel/yosys/Makefile
  head/devel/yosys/distinfo
  head/devel/yosys/pkg-descr
  head/devel/yosys/pkg-plist