Bug 247576
| Summary: | [regression] v356609 breaks i2c on Allwinner H5 | ||||||||
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| Product: | Base System | Reporter: | Manuel Stühn <freebsd> | ||||||
| Component: | arm | Assignee: | freebsd-arm (Nobody) <freebsd-arm> | ||||||
| Status: | Closed FIXED | ||||||||
| Severity: | Affects Only Me | CC: | manu | ||||||
| Priority: | --- | ||||||||
| Version: | CURRENT | ||||||||
| Hardware: | Any | ||||||||
| OS: | Any | ||||||||
| Attachments: |
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Description
Manuel Stühn
2020-06-27 08:50:53 UTC
Created attachment 216223 [details]
Fix twsi bug
Could you test the attached patch ?
This fix two things :
When we don't receive an ack we still send a stop bit, some (most/all ?) device don't send a ack for the last transmitted bit. Not doing this make the controller goes crazy.
Some IP (Like H3/H5) have a bug where we need to write to the control register with the interrupt enabled flag after each interrupts have fired once.
This patch works for me. Thank you! (In reply to Manuel Stühn from comment #2) That's good that it works for you but it's still not good :) I've fixed more bug and will post a new patch tonight (even if not finished). Created attachment 216261 [details]
Fix twsi bug
Could you test this patch too ?
I still have weird stuff happening but it might be that I'm not talking correctly to the device.
Also the new patch works (was the eeprom@50 change in sun8i-h3-i2c0.dtso intentional?). Nevertheless, i2c -s finds the display at address 0x3C and to the display can be written to. Thanks again. (In reply to Manuel Stühn from comment #5) No the dtso was just a local change that I included by mistake. Thanks for testing, I'll do more work into this and will commit a proper version before saturday after more testing. A commit references this bug: Author: manu Date: Wed Jul 8 19:14:44 UTC 2020 New revision: 363021 URL: https://svnweb.freebsd.org/changeset/base/363021 Log: twsi: Fix for > Allwinner A20 Every revision of twsi after the A20 have a bug where we need to write again the control register after each interrupts. We also need to add some delay before writing to this register, a simple read of the same register does the job so do that. Also fix the case when we have finish sending all the bytes, it only worked for 1 byte transfer (the same kind that we do for talking to the PMIC on A20 boards). While here add more debug messages and rework some of them. This was tested by talking to a AT23C32 eeprom and a DS3231 RTC from an H3 and A20 board. PR: 247576 Reported by: Manuel St?hn (freebsd@justmail.de) MFC after: 1 week Changes: head/sys/dev/iicbus/twsi/twsi.c Tested the commited revision. Works fine for me. Thanks again. A commit references this bug: Author: avg Date: Mon Oct 12 11:34:09 UTC 2020 New revision: 366645 URL: https://svnweb.freebsd.org/changeset/base/366645 Log: MFC r363021 by manu: twsi: Fix for > Allwinner A20 Every revision of twsi after the A20 have a bug where we need to write again the control register after each interrupts. We also need to add some delay before writing to this register, a simple read of the same register does the job so do that. Also fix the case when we have finish sending all the bytes, it only worked for 1 byte transfer (the same kind that we do for talking to the PMIC on A20 boards). While here add more debug messages and rework some of them. This was tested by talking to a AT23C32 eeprom and a DS3231 RTC from an H3 and A20 board. PR: 247576 Changes: _U stable/12/ stable/12/sys/dev/iicbus/twsi/twsi.c |
