Summary: | panic: Unknown userland exception 4, trap value 27bd3 | ||
---|---|---|---|
Product: | Base System | Reporter: | P1umer <p1umer1337> |
Component: | kern | Assignee: | Mitchell Horne <mhorne> |
Status: | Closed FIXED | ||
Severity: | Affects Only Me | CC: | emaste, mhorne |
Priority: | --- | ||
Version: | CURRENT | ||
Hardware: | riscv | ||
OS: | Any | ||
URL: | https://reviews.freebsd.org/D36876 |
Description
P1umer
2022-08-30 03:57:28 UTC
*** Bug 266110 has been marked as a duplicate of this bug. *** A commit in branch main references this bug: URL: https://cgit.FreeBSD.org/src/commit/?id=9b4cbaa9c3da233cf06381c3d22e3472ee586585 commit 9b4cbaa9c3da233cf06381c3d22e3472ee586585 Author: Mitchell Horne <mhorne@FreeBSD.org> AuthorDate: 2022-10-11 13:39:50 +0000 Commit: Mitchell Horne <mhorne@FreeBSD.org> CommitDate: 2022-10-11 13:39:50 +0000 riscv: handle misaligned address exceptions If this exception is coming from userspace, send the appropriate SIGBUS to the process. If it's coming from the kernel this is still fatal, but we can give a better panic message. Typical misaligned loads/stores are emulated by the SBI firmware, and require no intervention from our kernel. The notable exception here is misaligned access with atomic instructions. These can generate the exception and panic seen in the PR. With this, we now handle all defined exception types. PR: 266109 MFC after: 1 week Found by: syzkaller Reported by: P1umer <p1umer1337@gmail.com> Differential Revision: https://reviews.freebsd.org/D36876 sys/riscv/riscv/trap.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) A commit in branch stable/13 references this bug: URL: https://cgit.FreeBSD.org/src/commit/?id=97edb6baa91096a2d7d37546ad59596abe5c5b1b commit 97edb6baa91096a2d7d37546ad59596abe5c5b1b Author: Mitchell Horne <mhorne@FreeBSD.org> AuthorDate: 2022-10-11 13:39:50 +0000 Commit: Mitchell Horne <mhorne@FreeBSD.org> CommitDate: 2022-10-18 14:08:22 +0000 riscv: handle misaligned address exceptions If this exception is coming from userspace, send the appropriate SIGBUS to the process. If it's coming from the kernel this is still fatal, but we can give a better panic message. Typical misaligned loads/stores are emulated by the SBI firmware, and require no intervention from our kernel. The notable exception here is misaligned access with atomic instructions. These can generate the exception and panic seen in the PR. With this, we now handle all defined exception types. PR: 266109 MFC after: 1 week Found by: syzkaller Reported by: P1umer <p1umer1337@gmail.com> Differential Revision: https://reviews.freebsd.org/D36876 (cherry picked from commit 9b4cbaa9c3da233cf06381c3d22e3472ee586585) sys/riscv/riscv/trap.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) |