Bug 75898

bsd.cpu.mk as of version 1.42 on 6.0-CURRENT and 1.40.2.1 on 5.3-STABLE recognizes the setting CPUTYPE=pentium-m in /etc/make.conf, which enables code generation and optimization for the Pentium M family. One of the features enabled by this switch is SSE2. This works fine once the systems is up and running, but breaks the boot process.

The problem is that for SSE and SSE2 instructions to be available, the OSFXSR bit in CR4 must be set. This has to be done by the operating system, as the bit is off by default. At system startup, the kernel sets the bit at some point. However, the code that runs before this point in time already tries to use SSE2 instructions and fails miserably with an UD exception (invalid opcode), which in turn leads to an instant reboot.

The code that runs before the OSFXSR bit is set is the entire loader  and part of the kernel.

To confirm that the problems lies in SSE2 instructions being used too early, I recompiled with CPUTYPE=pentium3 and the system started up as expected. Others have reported the same issue with CPUTYPE=athlon-xp, which also has SSE support. It might be that some motherboards silently set OSFXSR, in which case this problem would not appear on the respective systems and therefore is a bit hard to chase.

Fix: 

One way of fixing this would be to specifically disable SSE and SSE2 support in the Makefiles of those parts of the system that run before the OSFXSR bit is set. However, it might be hard to find all the Makefiles and to maintain those fixes over a long time.

Another way would be to enable the OSFXSR bit earlier on in the boot process. NOTE however that this bit also indicates that XMM registers are saved on context switch, so with setting this bit comes the obligation to always used FXSAVE and FXRSTOR.
How-To-Repeat: * Build world and / or kernel on a machine with above mentioned version of bsd.cpu.mk and CPUTYPE=pentium-m
* Reboot
* If the BIOS does not set OSFXSR in CR4, watch the UD exception and the instant reboot