The Verilog-Perl library is a building point for Verilog support in the Perl language.
Fix: Patch attached with submission follows:
I'll take it.
This port has some common problems, please, install ports-mgmt/porttools and
after run following command inside port directory:
More information can be found on Porters Handbook .
Please, fix it and send a new shar as a followup on this PR.
 - http://www.freebsd.org/doc/en/books/porters-handbook/
Renato Botelho <garga @ FreeBSD.org>
<garga @ freebsdbrasil.com.br>
GnuPG Key: http://www.FreeBSD.org/~garga/pubkey.asc
They are called computers simply because computation is
the only significant job that has so far been given to them.
Ask for submitter fix.
New port added. Thanks!
garga 2009-05-26 11:01:39 UTC
FreeBSD ports repository
cad/p5-Verilog-Perl Makefile distinfo pkg-descr pkg-plist
The Verilog-Perl library is a building point for Verilog support in the Perl
language. It includes:
* Verilog::Getopt which parses command line options similar to C++ and VCS.
* Verilog::Language which knows the language keywords and parses numbers.
* Verilog::Netlist which builds netlists out of Verilog files. This allows
easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser invokes callbacks for language tokens.
* Verilog::Preproc preprocesses the language, and allows reading
post-processed files right from Perl without temporary files.
* vpassert inserts PLIish warnings and assertions for any simulator.
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
cross references and makes it easy to rename signal and module names across
multiple files. Vrename uses a simple and efficient three step process.
First, you run vrename to create a list of signals in the design. You then
edit this list, changing as many symbols as you wish. Vrename is then run a
second time to apply the changes.
Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto at ee.ufcg.edu.br>
Revision Changes Path
1.108 +1 -0 ports/cad/Makefile
1.1 +42 -0 ports/cad/p5-Verilog-Perl/Makefile (new)
1.1 +3 -0 ports/cad/p5-Verilog-Perl/distinfo (new)
1.1 +19 -0 ports/cad/p5-Verilog-Perl/pkg-descr (new)
1.1 +33 -0 ports/cad/p5-Verilog-Perl/pkg-plist (new)
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