The UltraSPARC architecture implements IEEE Std 754-1985 using a combination of hardware and software - specific implementations will typically implement a subset of the standard in hardware and trap on other floating point operations to allow software emulation. In order to meet this requirement, FreeBSD provides a complete (though SPARC-oriented) floating-point emulator. Initial errors reported by one of perl's configuration tools led me to undertake a more rigorous examination of FreeBSD's emulator. Whilst some gross errors were recently corrected in r204974 & r205002, an IEEE test (http://www.jhauser.us/arithmetic/TestFloat.html) reported a significant number of errors. The attached patch comprises patches to the sparc64 userland floating point code, together with a test harness (based on TestFloat above) to verify the correct operation of the floating point code. Whilst the test harness currently only includes sparc64 support, extending it to other architectures should be simple. Explanation of the fixes: - libc/softfloat is used by the test harness code. It defaults to detecting tinyness after rounding whilst the UltraSPARC Architecture document states that the UltraSPARC detects tinyness before rounding. A patch to softfloat-specialize changes this for sparc only. - Parts of the emulator code must be compiled with no-strict-aliasing specified to function correctly. CFLAGS is updated to include the relevant gcc option. (This will add -fno-strict-aliasing to all of libc - which is excessive but I don't believe it's possible to compile only part of libc that way). - When FPU_DEBUG is defined, files using the debugging facilities need stdio defined. - Division should take both argument's signs into account when the dividend is infinity or zero and the divisor is not the same. - Add a note that the emulator code depends on the numeric values of the FTYPE_xxx macros in places. - __fpu_ftox() needs to correctly return overflow in two pieces. - The UltraSPARC architecture defines that tinyness is detected before rounding therefore rounding up to the smallest normalised number should set the underflow flag. - If an infinite result is rounded down, the result should have an exponent 1 less than the value for infinity. Fix: [Test harness will be forwarded separately] How-To-Repeat: Run the test harness without applying the emulator fixes: cd /usr/src/tools/test/testfloat/sparc64 make obj && make depend && make cd /usr/obj/usr/src/tools/test/testfloat/sparc64 ./testsoftfloat -all 2>/dev/null # Verify that "No errors found" is reported for all tests ./testemufloat -all 2>/dev/null # Verify that a variety of errors are reported ./testsoftfloat -all 2>/dev/null # Verify that a variety of errors are reported (Explanation of the test error output can be found in /usr/src/tools/test/testfloat/testfloat.txt). Apply emulator fixes and rebuild the test harness. If the above tests are rerun, testsoftfloat and testemufloat should report no errors. testfloat will continue to report errors because libc hasn't been rebuilt. Rebuild and re-install libc. Rerun testfloat and it should report no errors. More rigorous testing is possible by adding '-level 2' prior to '-all' but this will take many hours to run.
On Sat, Mar 20, 2010 at 08:11:20PM +1100, Peter Jeremy wrote: > - Parts of the emulator code must be compiled with no-strict-aliasing > specified to function correctly. CFLAGS is updated to include the > relevant gcc option. (This will add -fno-strict-aliasing to all of > libc - which is excessive but I don't believe it's possible to compile > only part of libc that way). Could you please elaborate on what exactly breaks when compiling with strict aliasing rules? I think there actually is a way to limit -no-strict-aliasing to the emulator part but I'd like to understand what's going on and make sure there's no way it can be solved by the code affected before turning it on. Marius
The test harness referred to in the PR is too big to directly attach to the PR and is available for download in either shar or tar format: http://members.optusnet.com.au/peterjeremy/sparc_test.tar.bz2 http://members.optusnet.com.au/peterjeremy/sparc_test.shar and have the following checksums: MD5 (sparc_test.shar) = 9c6931df23ff51805c20fb60055092d1 SHA256 (sparc_test.shar) = 8ca68447a04c0551712bf5f5f111be7b55f48c0a33f3f07a73010c2209b8b871 MD5 (sparc_test.tar.bz2) = 1eb78c608e3b3f0dc77f3d866edfd499 SHA256 (sparc_test.tar.bz2) = e018fa3ac72179cdb71863ce82d71540cb304d87e9efeac71ad45a17c7c06731 -- Peter Jeremy
Author: marius Date: Sat Mar 20 21:15:56 2010 New Revision: 205394 URL: http://svn.freebsd.org/changeset/base/205394 Log: Ensure that __fpu_ftox() both returns the high bits and res[1] contains the low bits also in the default case. PR: 144900 Obtained from: OpenBSD MFC after: 3 days Modified: head/lib/libc/sparc64/fpu/fpu_implode.c Modified: head/lib/libc/sparc64/fpu/fpu_implode.c ============================================================================== --- head/lib/libc/sparc64/fpu/fpu_implode.c Sat Mar 20 21:04:47 2010 (r205393) +++ head/lib/libc/sparc64/fpu/fpu_implode.c Sat Mar 20 21:15:56 2010 (r205394) @@ -248,8 +248,8 @@ __fpu_ftox(fe, fp, res) sign = fp->fp_sign; switch (fp->fp_class) { case FPC_ZERO: - res[1] = 0; - return (0); + i = 0; + goto done; case FPC_NUM: /* @@ -273,15 +273,17 @@ __fpu_ftox(fe, fp, res) break; if (sign) i = -i; - res[1] = (int)i; - return (i >> 32); + goto done; default: /* Inf, qNaN, sNaN */ break; } /* overflow: replace any inexact exception with invalid */ fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; - return (0x7fffffffffffffffLL + sign); + i = 0x7fffffffffffffffLL + sign; +done: + res[1] = i & 0xffffffff; + return (i >> 32); } /* _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Sat Mar 20 21:27:44 2010 New Revision: 205395 URL: http://svn.freebsd.org/changeset/base/205395 Log: FPU_DEBUG requires <stdio.h>. PR: 144900 Submitted by: Peter Jeremy MFC after: 3 days Modified: head/lib/libc/sparc64/fpu/fpu.c head/lib/libc/sparc64/fpu/fpu_explode.c head/lib/libc/sparc64/fpu/fpu_implode.c Modified: head/lib/libc/sparc64/fpu/fpu.c ============================================================================== --- head/lib/libc/sparc64/fpu/fpu.c Sat Mar 20 21:15:56 2010 (r205394) +++ head/lib/libc/sparc64/fpu/fpu.c Sat Mar 20 21:27:44 2010 (r205395) @@ -69,9 +69,12 @@ __FBSDID("$FreeBSD$"); #include "namespace.h" #include <errno.h> -#include <unistd.h> #include <signal.h> +#ifdef FPU_DEBUG +#include <stdio.h> +#endif #include <stdlib.h> +#include <unistd.h> #include "un-namespace.h" #include "libc_private.h" Modified: head/lib/libc/sparc64/fpu/fpu_explode.c ============================================================================== --- head/lib/libc/sparc64/fpu/fpu_explode.c Sat Mar 20 21:15:56 2010 (r205394) +++ head/lib/libc/sparc64/fpu/fpu_explode.c Sat Mar 20 21:27:44 2010 (r205395) @@ -49,6 +49,10 @@ __FBSDID("$FreeBSD$"); #include <sys/param.h> +#ifdef FPU_DEBUG +#include <stdio.h> +#endif + #include <machine/frame.h> #include <machine/fp.h> #include <machine/fsr.h> Modified: head/lib/libc/sparc64/fpu/fpu_implode.c ============================================================================== --- head/lib/libc/sparc64/fpu/fpu_implode.c Sat Mar 20 21:15:56 2010 (r205394) +++ head/lib/libc/sparc64/fpu/fpu_implode.c Sat Mar 20 21:27:44 2010 (r205395) @@ -49,6 +49,10 @@ __FBSDID("$FreeBSD$"); #include <sys/param.h> +#ifdef FPU_DEBUG +#include <stdio.h> +#endif + #include <machine/frame.h> #include <machine/fp.h> #include <machine/fsr.h> _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Sat Mar 20 22:12:15 2010 New Revision: 205396 URL: http://svn.freebsd.org/changeset/base/205396 Log: Division should take both arguments' signs into account when the the dividend is infinity or zero and the divisor is not the same. PR: 144900 Submitted by: Peter Jeremy MFC after: 3 days Modified: head/lib/libc/sparc64/fpu/fpu_div.c Modified: head/lib/libc/sparc64/fpu/fpu_div.c ============================================================================== --- head/lib/libc/sparc64/fpu/fpu_div.c Sat Mar 20 21:27:44 2010 (r205395) +++ head/lib/libc/sparc64/fpu/fpu_div.c Sat Mar 20 22:12:15 2010 (r205396) @@ -167,14 +167,16 @@ __fpu_div(fe) * return it. Otherwise we have the following cases: * * Inf / Inf = NaN, plus NV exception - * Inf / num = Inf [i.e., return x] - * Inf / 0 = Inf [i.e., return x] - * 0 / Inf = 0 [i.e., return x] - * 0 / num = 0 [i.e., return x] + * Inf / num = Inf [i.e., return x #] + * Inf / 0 = Inf [i.e., return x #] + * 0 / Inf = 0 [i.e., return x #] + * 0 / num = 0 [i.e., return x #] * 0 / 0 = NaN, plus NV exception - * num / Inf = 0 + * num / Inf = 0 # * num / num = num (do the divide) - * num / 0 = Inf, plus DZ exception + * num / 0 = Inf #, plus DZ exception + * + * # Sign of result is XOR of operand signs. */ if (ISNAN(x) || ISNAN(y)) { ORDER(x, y); @@ -183,10 +185,10 @@ __fpu_div(fe) if (ISINF(x) || ISZERO(x)) { if (x->fp_class == y->fp_class) return (__fpu_newnan(fe)); + x->fp_sign ^= y->fp_sign; return (x); } - /* all results at this point use XOR of operand signs */ x->fp_sign ^= y->fp_sign; if (ISINF(y)) { x->fp_class = FPC_ZERO; _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Sat Mar 20 22:32:13 2010 New Revision: 205397 URL: http://svn.freebsd.org/changeset/base/205397 Log: - While SPARC V9 allows tininess to be detected either before or after rounding (impl. dep. #55), the SPARC JPS1 responsible for SPARC64 and UltraSPARC processors defines that in all cases tinyness is detected before rounding, therefore rounding up to the smallest normalised number should set the underflow flag. - If an infinite result is rounded down, the result should have an exponent 1 less than the value for infinity. PR: 144900 Submitted by: Peter Jeremy MFC after: 3 days Modified: head/lib/libc/sparc64/fpu/fpu_implode.c Modified: head/lib/libc/sparc64/fpu/fpu_implode.c ============================================================================== --- head/lib/libc/sparc64/fpu/fpu_implode.c Sat Mar 20 22:12:15 2010 (r205396) +++ head/lib/libc/sparc64/fpu/fpu_implode.c Sat Mar 20 22:32:13 2010 (r205397) @@ -329,8 +329,9 @@ __fpu_ftos(fe, fp) * right to introduce leading zeroes. Rounding then acts * differently for normals and subnormals: the largest subnormal * may round to the smallest normal (1.0 x 2^minexp), or may - * remain subnormal. In the latter case, signal an underflow - * if the result was inexact or if underflow traps are enabled. + * remain subnormal. A number that is subnormal before rounding + * will signal an underflow if the result is inexact or if underflow + * traps are enabled. * * Rounding a normal, on the other hand, always produces another * normal (although either way the result might be too big for @@ -345,8 +346,10 @@ __fpu_ftos(fe, fp) if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ (void) __fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); - if (fpround(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) + if (fpround(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) { + fe->fe_cx |= FSR_UF; return (sign | SNG_EXP(1) | 0); + } if ((fe->fe_cx & FSR_NX) || (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) fe->fe_cx |= FSR_UF; @@ -407,6 +410,7 @@ zero: res[1] = 0; if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { (void) __fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); if (fpround(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { + fe->fe_cx |= FSR_UF; res[1] = 0; return (sign | DBL_EXP(1) | 0); } @@ -426,7 +430,7 @@ zero: res[1] = 0; return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); } res[1] = ~0; - return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); + return (sign | DBL_EXP(DBL_EXP_INFNAN - 1) | DBL_MASK); } done: res[1] = fp->fp_mant[3]; @@ -468,6 +472,7 @@ zero: res[1] = res[2] = res[3] = 0; if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) { (void) __fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp); if (fpround(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) { + fe->fe_cx |= FSR_UF; res[1] = res[2] = res[3] = 0; return (sign | EXT_EXP(1) | 0); } @@ -487,7 +492,7 @@ zero: res[1] = res[2] = res[3] = 0; return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0); } res[1] = res[2] = res[3] = ~0; - return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK); + return (sign | EXT_EXP(EXT_EXP_INFNAN - 1) | EXT_MASK); } done: res[1] = fp->fp_mant[1]; _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
On 2010-Mar-20 21:49:41 +0100, Marius Strobl <marius@alchemy.franken.de> wrote: >On Sat, Mar 20, 2010 at 08:11:20PM +1100, Peter Jeremy wrote: >> - Parts of the emulator code must be compiled with no-strict-aliasing >> specified to function correctly. CFLAGS is updated to include the >> relevant gcc option. (This will add -fno-strict-aliasing to all of >> libc - which is excessive but I don't believe it's possible to compile >> only part of libc that way). > >Could you please elaborate on what exactly breaks when compiling >with strict aliasing rules? I think there actually is a way to >limit -no-strict-aliasing to the emulator part but I'd like to >understand what's going on and make sure there's no way it can >be solved by the code affected before turning it on. The problem manifests in a number of seemingly unrelated ways. The obvious aliasing issues (from code examination) are in fpu_explode.c and union-based aliasing in fpu_qp.c. It appears that compiling just fpu_explode.c with -fno-strict-aliasing is sufficient to make the errors go away. This suggests that the problem may be amenable to code patching. The following errors are reported by 'testemufloat -all' (I've pruned the list of reported errors to shorten this mail). The FP format is defined in testfloat/testfloat.txt but an overview is: Single precision: x000 .... .... . .... .... .... .... .... .... sign (1 bit) .... xxxx xxxx . .... .... .... .... .... .... exponent (8 bits) .... .... .... . 0xxx xxxx xxxx xxxx xxxx xxxx fraction (23 bits) For double and long double precision, the '.' is located between the exponent and fraction, with the top bit of the exponent representing the sign. In all cases, the implicit '1' is not shown. The 5-char field represents exception bits as follows: v invalid flag z division-by-zero flag o overflow flag u underflow flag x inexact flag In virtually all cases, the reported sign is incorrect. The errors in int64_to_float32, int64_to_float64, int64_to_float128, float64_sqrt, float128_to_float64, float128_add, float128_sub, float128_mul, float128_div, float128_sqrt, float128_eq, float128_le, float128_lt, float128_eq_signalling, float128_le_quiet and float128_lt_quiet otherwise appear random. The results are negated in float64_to_int32_round_to_zero, float64_to_int64_round_to_zero, float64_to_float32, float64_to_float128, float64_add, float64_sub, float64_mul, float64_div, float128_to_int32_round_to_zero, float128_to_int64_round_to_zero (though one result has the correct sign and just the low order 12 bits are incorrect) and float128_to_float32. The sign confusion appears to cause incorrect results in float64_eq, float64_le and float64_lt. Errors found in int64_to_float32, rounding nearest_even: FFFFFFFF85366D68 soft: 89D.759325 ....x syst: 0BF.000000 ....x 0000000000000000 soft: 000.000000 ..... syst: 800.000000 ..... FED98D1D7EA052A1 soft: 8B7.133971 ....x syst: 0BE.7ED98D ....x 0000000000000001 soft: 07F.000000 ..... syst: 87F.000000 ..... FFFE87E94EE94B0B soft: 8AF.3C0B59 ....x syst: 0BE.7FFE88 ....x 0000000000000002 soft: 080.000000 ..... syst: 880.000000 ..... F0D9B2277EDEB41E soft: 8BA.7264DE ....x syst: 0BE.70D9B2 ....x 0000000000000004 soft: 081.000000 ..... syst: 881.000000 ..... FEFFFFFE3FFFFFFF soft: 8B7.000001 ....x syst: 0BE.7F0000 ....x 0000000000000020 soft: 084.000000 ..... syst: 884.000000 ..... Errors found in int64_to_float32, rounding to_zero: Errors found in int64_to_float32, rounding down: Errors found in int64_to_float32, rounding up: Errors found in int64_to_float64, rounding nearest_even: 800021FFFFFFFFFD soft: C3D.FFFF780000000 ....x syst: 43E.0000440000000 ....x 000000000000000A soft: 402.4000000000000 ..... syst: C02.4000000000000 ..... FBFFFFFFFF7FF7FE soft: C39.0000000020020 ....x syst: 43E.F7FFFFFFFEFFF ....x 0000000000000002 soft: 400.0000000000000 ..... syst: C00.0000000000000 ..... C0007FFE00000000 soft: C3C.FFFC001000000 ..... syst: 43E.8000FFFC00000 ..... 0000000000000004 soft: 401.0000000000000 ..... syst: C01.0000000000000 ..... FFFFFFFFFFF003FE soft: C12.FF80400000000 ..... syst: 43E.FFFFFFFFFFE00 ....x 0000000000000010 soft: 403.0000000000000 ..... syst: C03.0000000000000 ..... FFFFFFFF781078B5 soft: C1E.0FDF0E9600000 ..... syst: 43E.FFFFFFFEF020F ....x 0000000000000020 soft: 404.0000000000000 ..... syst: C04.0000000000000 ..... Errors found in int64_to_float64, rounding to_zero: Errors found in int64_to_float64, rounding down: Errors found in int64_to_float64, rounding up: Errors found in int64_to_float128: FDFFFFF7EFFFFFFE soft: C038.0000040800000100000000000000 ..... syst: 403E.FBFFFFEFDFFFFFFC000000000000 ..... 0032A8E5535CD163 soft: 4034.95472A9AE68B1800000000000000 ..... syst: C034.95472A9AE68B1800000000000000 ..... FFFFFFFE07FFFFFE soft: C01F.F800000200000000000000000000 ..... syst: 403E.FFFFFFFC0FFFFFFC000000000000 ..... 00000000001C995A soft: 4013.C995A00000000000000000000000 ..... syst: C013.C995A00000000000000000000000 ..... FFFFFEF7FFFEFFFE soft: C027.0800010002000000000000000000 ..... syst: 403E.FFFFFDEFFFFDFFFC000000000000 ..... 0000000000000004 soft: 4001.0000000000000000000000000000 ..... syst: C001.0000000000000000000000000000 ..... 80000007FFFFFFFE soft: C03D.FFFFFFE000000008000000000000 ..... syst: 403E.0000000FFFFFFFFC000000000000 ..... 0000000000A597F0 soft: 4016.4B2FE00000000000000000000000 ..... syst: C016.4B2FE00000000000000000000000 ..... FFFFFEFFFFC3FFFE soft: C027.00003C0002000000000000000000 ..... syst: 403E.FFFFFDFFFF87FFFC000000000000 ..... 0000063A5D983DA5 soft: 4029.8E97660F69400000000000000000 ..... syst: C029.8E97660F69400000000000000000 ..... Errors found in float64_to_int32_round_to_zero: C3E.037FFFFFFFFFF soft: 80000000 v.... syst: 7FFFFFFF v.... 402.007FFFDFFFFFE soft: 00000008 ....x syst: FFFFFFF8 ....x C02.FFFFF800000FF soft: FFFFFFF1 ....x syst: 0000000F ....x C1D.278E6110DFB5B soft: B61C67BC ....x syst: 49E39844 ....x C0C.EFFFFDFFFFFFE soft: FFFFC201 ....x syst: 00003DFF ....x C1B.CF02007CC83D7 soft: E30FDFF9 ....x syst: 1CF02007 ....x C96.0000000004003 soft: 80000000 v.... syst: 7FFFFFFF v.... F72.C296F6303BAF4 soft: 80000000 v.... syst: 7FFFFFFF v.... E1A.0020100000000 soft: 80000000 v.... syst: 7FFFFFFF v.... C0D.FFFFE00000FFF soft: FFFF8001 ....x syst: 00007FFF ....x Errors found in float64_to_int64_round_to_zero: C85.0000000000F7E soft: 8000000000000000 v.... syst: 7FFFFFFFFFFFFFFF v.... BFF.FFF00000000FF soft: FFFFFFFFFFFFFFFF ....x syst: 0000000000000001 ....x C02.FFF80000003FF soft: FFFFFFFFFFFFFFF1 ....x syst: 000000000000000F ....x C3D.0000000801000 soft: BFFFFFFDFFC00000 ..... syst: 4000000200400000 ..... C1C.000009FFFFFFF soft: FFFFFFFFDFFFFEC1 ....x syst: 000000002000013F ....x C03.80F104A1FA39D soft: FFFFFFFFFFFFFFE8 ....x syst: 0000000000000018 ....x C00.0000000010003 soft: FFFFFFFFFFFFFFFE ....x syst: 0000000000000002 ....x F5D.35B4561B01C9C soft: 8000000000000000 v.... syst: 7FFFFFFFFFFFFFFF v.... C3D.FF801FFFFFFFF soft: 801FF80000000400 ..... syst: 7FE007FFFFFFFC00 ..... C03.705F27662F75B soft: FFFFFFFFFFFFFFE9 ....x syst: 0000000000000017 ....x Errors found in float64_to_float32, rounding nearest_even: BCA.0004000FFFFFF soft: 84A.000200 ....x syst: 04A.000200 ....x 000.0000000000000 soft: 000.000000 ..... syst: 800.000000 ..... C33.6B3CFC1374734 soft: 8B3.359E7E ....x syst: 0B3.359E7E ....x 000.0000000000001 soft: 000.000000 ...ux syst: 800.000000 ...ux BFD.42DB4573445CA soft: 87D.216DA3 ....x syst: 07D.216DA3 ....x 001.FFFFFFFF01FFE soft: 000.000000 ...ux syst: 800.000000 ...ux CEB.EFFFFFFFFF7FF soft: 8FF.000000 ..o.x syst: 0FF.000000 ..o.x 001.0000000000000 soft: 000.000000 ...ux syst: 800.000000 ...ux C1C.0300000000000 soft: 89C.018000 ..... syst: 09C.018000 ..... 001.0000000000001 soft: 000.000000 ...ux syst: 800.000000 ...ux Errors found in float64_to_float32, rounding to_zero: Errors found in float64_to_float32, rounding down: Errors found in float64_to_float32, rounding up: Errors found in float64_to_float128: C0C.0000000000041 soft: C00C.0000000000041000000000000000 ..... syst: 400C.0000000000041000000000000000 ..... 3F6.000000000FFFB soft: 3FF6.000000000FFFB000000000000000 ..... syst: BFF6.000000000FFFB000000000000000 ..... C18.FFFC000FFFFFF soft: C018.FFFC000FFFFFF000000000000000 ..... syst: 4018.FFFC000FFFFFF000000000000000 ..... 000.0000000000001 soft: 3BCD.0000000000000000000000000000 ..... syst: BBCD.0000000000000000000000000000 ..... C3D.0407FFFFFFFFE soft: C03D.0407FFFFFFFFE000000000000000 ..... syst: 403D.0407FFFFFFFFE000000000000000 ..... 480.0010008000000 soft: 4080.0010008000000000000000000000 ..... syst: C080.0010008000000000000000000000 ..... D76.00200000003FF soft: C176.00200000003FF000000000000000 ..... syst: 4176.00200000003FF000000000000000 ..... 000.FFFFFFFFFFFFE soft: 3C00.FFFFFFFFFFFFC000000000000000 ..... syst: BC00.FFFFFFFFFFFFC000000000000000 ..... 800.9A9E51A5E8212 soft: BC00.353CA34BD0424000000000000000 ..... syst: 3C00.353CA34BD0424000000000000000 ..... 001.0000000000000 soft: 3C01.0000000000000000000000000000 ..... syst: BC01.0000000000000000000000000000 ..... Errors found in float64_add, rounding nearest_even: C02.A3E7A164FE784 001.FFFFF80000000 soft: C02.A3E7A164FE784 ....x syst: 402.A3E7A164FE784 ....x C3D.0000000000011 000.0000000000000 soft: C3D.0000000000011 ..... syst: 43D.0000000000011 ..... 41F.AAA39D0D72647 C67.FFFFFFEFFFF7E soft: C67.FFFFFFEFFFF7E ....x syst: 467.FFFFFFEFFFF7E ....x 2AE.FC000000003FF C01.000000001FFFD soft: C01.000000001FFFD ....x syst: 401.000000001FFFD ....x 000.0000000000000 BFF.003FFF7FFFFFF soft: BFF.003FFF7FFFFFF ..... syst: 3FF.003FFF7FFFFFF ..... 402.380973C6BD218 B37.00000000001FE soft: 402.380973C6BD218 ....x syst: C02.380973C6BD218 ....x 3CA.FFF8000008000 C1F.0001FFFFFFC00 soft: C1F.0001FFFFFFC00 ....x syst: 41F.0001FFFFFFC00 ....x C08.0000000000000 3FE.2A015D953FF0D soft: C07.FF6AFF5135600 ....x syst: 407.FF6AFF5135600 ....x 000.0000000000000 BCA.00000087FFFFE soft: BCA.00000087FFFFE ..... syst: 3CA.00000087FFFFE ..... 3FD.FDFFF7FFFFFFF C1F.FFFFFFAFFFFFF soft: C1F.FFFFFFAF807FF ....x syst: 41F.FFFFFFB07F7FF ....x Errors found in float64_add, rounding to_zero: Errors found in float64_add, rounding down: Errors found in float64_add, rounding up: Errors found in float64_sub, rounding nearest_even: Errors found in float64_sub, rounding to_zero: Errors found in float64_sub, rounding down: Errors found in float64_sub, rounding up: Errors found in float64_mul, rounding nearest_even: E37.08001FFFFFFFE EC7.FFFFFEEFFFFFE soft: 7FF.0000000000000 ..o.x syst: FFF.0000000000000 ..o.x C1E.CAAFB2A53DFDD 000.0000000000000 soft: 800.0000000000000 ..... syst: 000.0000000000000 ..... C3F.00000000001FB FFE.FFC000000000F soft: 7FF.0000000000000 ..o.x syst: FFF.0000000000000 ..o.x 000.0000000000000 3FB.003FFFFFFE000 soft: 000.0000000000000 ..... syst: 800.0000000000000 ..... 41D.3069CE4DE50E6 C3E.CB2A5736C8D6A soft: C5D.110006FB4E5C2 ....x syst: 45D.110006FB4E5C2 ....x C1C.FB308867716C9 47D.3C2357C57B325 soft: C9B.392AF6F38A775 ....x syst: 49B.392AF6F38A775 ....x 482.FBBFFFFFFFFFE C2F.E6F908143F31D soft: CB3.E2EE36E3142B6 ....x syst: 4B3.E2EE36E3142B6 ....x 000.0000000000000 000.FFFFFFFFFFFFF soft: 000.0000000000000 ..... syst: 800.0000000000000 ..... 43F.07FFFFFEFFFFE BFC.00000007FFFFE soft: C3C.080000073FFFC ....x syst: 43C.080000073FFFC ....x 000.0000000000000 000.000000001F000 soft: 000.0000000000000 ..... syst: 800.0000000000000 ..... Errors found in float64_mul, rounding to_zero: Errors found in float64_mul, rounding down: Errors found in float64_mul, rounding up: Errors found in float64_div, rounding nearest_even: 000.0000000000000 401.8000000000006 soft: 000.0000000000000 ..... syst: 800.0000000000000 ..... C96.100000007FFFE C0E.000003FFFF7FF soft: 487.0FFFFBC08098F ....x syst: C87.0FFFFBC08098F ....x 000.0000000000000 C0C.0002000003FFF soft: 800.0000000000000 ..... syst: 000.0000000000000 ..... B81.000000400000E 41C.4298E74AE88EC soft: B63.964D60923F428 ....x syst: 363.964D60923F428 ....x 55B.00FFFFFFFFFF6 D67.C6F4E731E7DE7 soft: BF2.213920E70652F ....x syst: 3F2.213920E70652F ....x 000.0000000000000 000.0000000000001 soft: 000.0000000000000 ..... syst: 800.0000000000000 ..... 3F7.FFF7FFFFFFFF8 BE6.00007FFFFBFFF soft: C10.FFF7000487FD4 ....x syst: 410.FFF7000487FD4 ....x FFD.DCCDF02AB3541 000.FFFFFFFFFFFFF soft: FFF.0000000000000 ..o.x syst: 7FF.0000000000000 ..o.x FFE.00000FFFF0000 BFF.61AEAE4BAB191 soft: 7FD.7297C092B6353 ....x syst: FFD.7297C092B6353 ....x 000.0000000000000 000.FFFFFFFFFFFFF soft: 000.0000000000000 ..... syst: 800.0000000000000 ..... Errors found in float64_div, rounding to_zero: Errors found in float64_div, rounding down: Errors found in float64_div, rounding up: Errors found in float64_sqrt, rounding nearest_even: 98A.FFFFFC0000007 soft: 7FF.FFFFFFFFFFFFF v.... syst: 2C4.FFFFFDFFFFFF3 ....x 000.0000000000001 soft: 1E6.0000000000000 ..... syst: 7FF.FFFFFFFFFFFFF v.... C01.3F2E87BAD2B37 soft: 7FF.FFFFFFFFFFFFF v.... syst: 400.1DD9BCDF402B2 ....x 43C.77FFFFFFFFFFF soft: 41D.B6C30B83593E6 ....x syst: 7FF.FFFFFFFFFFFFF v.... 802.0008020000000 soft: 7FF.FFFFFFFFFFFFF v.... syst: 200.6A0F8FEE41785 ....x 000.FFFFFFFFFFFFE soft: 1FF.FFFFFFFFFFFFE ....x syst: 7FF.FFFFFFFFFFFFF v.... C26.7A017BDD4D83E soft: 7FF.FFFFFFFFFFFFF v.... syst: 412.B7EE3E6633D68 ....x 3CA.FFFFFFE00003F soft: 3E4.FFFFFFF00001F ....x syst: 7FF.FFFFFFFFFFFFF v.... BFC.FFFFFFC001FFF soft: 7FF.FFFFFFFFFFFFF v.... syst: 3FD.FFFFFFE000FFF ....x 432.0001FFFFFFFF7 soft: 418.6A0B507125202 ....x syst: 7FF.FFFFFFFFFFFFF v.... Errors found in float64_sqrt, rounding to_zero: Errors found in float64_sqrt, rounding down: Errors found in float64_sqrt, rounding up: Errors found in float64_eq: 000.0000000000001 800.0000000000001 soft: 0 ..... syst: 1 ..... 000.FFFFFFFFFFFFF 000.FFFFFFFFFFFFF soft: 1 ..... syst: 0 ..... 000.FFFFFFFFFFFFF 800.FFFFFFFFFFFFF soft: 0 ..... syst: 1 ..... 000.FFFFFFFFFFFFE 000.FFFFFFFFFFFFE soft: 1 ..... syst: 0 ..... 000.FFFFFFFFFFFFE 800.FFFFFFFFFFFFE soft: 0 ..... syst: 1 ..... 001.0000000000000 001.0000000000000 soft: 1 ..... syst: 0 ..... 001.FFFFFFFFFFFFF 001.FFFFFFFFFFFFF soft: 1 ..... syst: 0 ..... 001.FFFFFFFFFFFFE 001.FFFFFFFFFFFFE soft: 1 ..... syst: 0 ..... 3CA.0000000000000 3CA.0000000000000 soft: 1 ..... syst: 0 ..... 3CA.0000000000000 BCA.0000000000000 soft: 0 ..... syst: 1 ..... Errors found in float64_le: C1F.FFEFBFFFFFFFF 434.FFFFEFFFFFFEF soft: 1 ..... syst: 0 ..... 000.0000000000000 C1E.FFC0000000010 soft: 0 ..... syst: 1 ..... 335.7FF7FFFFFFFFE 01E.FFFFFFFFE00FE soft: 0 ..... syst: 1 ..... 800.FFFFFFFFFFEBE 000.0000000000001 soft: 1 ..... syst: 0 ..... BFE.4C3DDC6ADA006 47E.FFF9FFFFFFFFE soft: 1 ..... syst: 0 ..... 800.3E0E8638E2CC3 3FB.0000000000040 soft: 1 ..... syst: 0 ..... 407.FFEF7FFFFFFFE 000.FFFFFFFFFFFFE soft: 0 ..... syst: 1 ..... C4A.0000DFFFFFFFE 480.DFE0000000000 soft: 1 ..... syst: 0 ..... 000.0000000000000 8BA.FB514E3B26DD2 soft: 0 ..... syst: 1 ..... 2FB.00FFF7FFFFFFF C1E.D431A58F6E9C1 soft: 0 ..... syst: 1 ..... Errors found in float64_lt: FFD.00000BFFFFFFF 480.0004000000100 soft: 1 ..... syst: 0 ..... 000.0000000000000 B7F.00000FF800000 soft: 0 ..... syst: 1 ..... 41F.A80E28C0BE462 04A.0803FFFFFFFFF soft: 0 ..... syst: 1 ..... 2D8.FFFFFFFFFFC02 C1E.8E253FD5983AF soft: 0 ..... syst: 1 ..... C0F.FFDFFFFFFEFFF 000.0000000000001 soft: 1 ..... syst: 0 ..... DB0.0000000007FFD 434.A6973C6DD3D3D soft: 1 ..... syst: 0 ..... 000.0000000000000 C0F.03FFFFFFFFFEF soft: 0 ..... syst: 1 ..... C03.0002000000010 000.FFFFFFFFFFFFF soft: 1 ..... syst: 0 ..... FFE.FFFFFC0000100 C07.FBFFFFFFEFFFF soft: 1 ..... syst: 0 ..... BFE.FFFFFFFFFE000 BFE.F6BCC606EC749 soft: 1 ..... syst: 0 ..... Errors found in float128_to_int32_round_to_zero: 0000.0000000000000000000000000000 soft: 00000000 ..... syst: 00000000 ....x C400.C5E7603B19AACCA31B9F7B5E42A2 soft: 80000000 v.... syst: 7FFFFFFF v.... C203.FF7FFFFFFFFFFFFFFFFFFFFFFFF8 soft: 80000000 v.... syst: 7FFFFFFF v.... C053.007FFFFFFFFFFFFFFFFFFFFFFFFF soft: 80000000 v.... syst: 7FFFFFFF v.... C000.FFFFFFFFFFFFFFFFFFFFFDFFFFFF soft: FFFFFFFD ....x syst: 00000003 ....x C2F8.0000000003FFFFFFFFFFFFFFFF7F soft: 80000000 v.... syst: 7FFFFFFF v.... 4005.FFFFBFFFFFFFFFFFFFFFFFFBFFFF soft: 0000007F ....x syst: FFFFFF81 ....x F66A.0000000000100000000000100000 soft: 80000000 v.... syst: 7FFFFFFF v.... C000.D289997D5CD5956A6E795F870D35 soft: FFFFFFFD ....x syst: 00000003 ....x D560.8063CE96B1AAFFEB394B49AE613D soft: 80000000 v.... syst: 7FFFFFFF v.... Errors found in float128_to_int64_round_to_zero: 0000.0000000000000000000000000000 soft: 0000000000000000 ..... syst: 0000000000000000 ....x C01C.FFEFFFFF00000000000000000000 soft: FFFFFFFFC0020001 ....x syst: 000000003FFDFFFF ....x 403C.EF5593056A34A3857765E0CB27C6 soft: 3DEAB260AD469470 ....x syst: 3DEAB260AD469FFF ....x BFFF.FFFFDE0000000000000000000000 soft: FFFFFFFFFFFFFFFF ....x syst: 0000000000000001 ....x C080.FFFF000000008000000000000000 soft: 8000000000000000 v.... syst: 7FFFFFFFFFFFFFFF v.... C03F.FFFFFFFFFFFFFEFFFFFFFFFFFFC0 soft: 8000000000000000 v.... syst: 7FFFFFFFFFFFFFFF v.... 3FFF.FFFF7FFFFFFFFF80000000000000 soft: 0000000000000001 ....x syst: FFFFFFFFFFFFFFFF ....x FFFD.FFF8000002000000000000000000 soft: 8000000000000000 v.... syst: 7FFFFFFFFFFFFFFF v.... C01F.FFFFFFFFFFFFFFFFFFFFFFF6FFFF soft: FFFFFFFE00000001 ....x syst: 00000001FFFFFFFF ....x BFFF.0000000002000000200000000000 soft: FFFFFFFFFFFFFFFF ....x syst: 0000000000000001 ....x Errors found in float128_to_float32, rounding nearest_even: 3F81.FFFFFFFFFFFFFFFFFFDFFFFFF000 soft: 002.000000 ....x syst: 802.000000 ....x 0000.0000000000000000000000000000 soft: 000.000000 ..... syst: 000.000000 ...ux B886.FFF2000000000000000000000000 soft: 800.000000 ...ux syst: 000.000000 ...ux 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFF soft: 000.000000 ...ux syst: 800.000000 ...ux BFF9.0000000000000000000100040000 soft: 879.000000 ....x syst: 079.000000 ....x 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFE soft: 000.000000 ...ux syst: 800.000000 ...ux C005.FFFFFFFFFFFFFFFFFFFFFF007FFF soft: 886.000000 ....x syst: 086.000000 ....x 3F80.00000000000000000FFFFFFFFFC0 soft: 000.400000 ...ux syst: 800.400000 ...ux 3F8E.FF00000000000000004000000000 soft: 00E.7F8000 ....x syst: 00E.7F8000 ..... 8001.97784557D9002A4B85519E04EB7C soft: 800.000000 ...ux syst: 000.000000 ...ux Errors found in float128_to_float32, rounding to_zero: Errors found in float128_to_float32, rounding down: Errors found in float128_to_float32, rounding up: Errors found in float128_to_float64, rounding nearest_even: 407E.0000000000007FFFFFFFFFFFC000 soft: 47E.0000000000008 ....x syst: 47E.0000000000000 ....x 0000.0000000000000000000000000000 soft: 000.0000000000000 ..... syst: 000.0000000000000 ...ux 407A.FFFFFFFFFFFFFFFFFFFFF0007FFF soft: 47B.0000000000000 ....x syst: 47A.FFFFFFFFFFFF0 ..... 4359.03FFFFF000000000000000000000 soft: 759.03FFFFF000000 ..... syst: 759.03FFFFF000010 ....x 0000.0000000000000000000000000001 soft: 000.0000000000000 ...ux syst: 000.0000000000000 ..... C002.FFFFFFFFFFFFFFFFFFEFFFFFFFFE soft: C03.0000000000000 ....x syst: 402.FFFFFFFFFFFF0 ....x 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFF soft: 000.0000000000000 ...ux syst: 800.0000000000000 ...ux 400E.FFFE000000000000000000000008 soft: 40E.FFFE000000000 ....x syst: 40E.FFFE000000010 ....x 8001.00000000000000000003FFF80000 soft: 800.0000000000000 ...ux syst: 000.0000000000000 ...ux 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFE soft: 000.0000000000000 ...ux syst: 800.0000000000000 ...ux Errors found in float128_to_float64, rounding to_zero: Errors found in float128_to_float64, rounding down: Errors found in float128_to_float64, rounding up: Errors found in float128_add, rounding nearest_even: BF21.FBFFFFFFFFFFFF00000000000000 BC00.0000001000000000000000000010 soft: BF21.FBFFFFFFFFFFFF00000000000000 ....x syst: 3F21.FBFFFFFFFFFF0000000040590867 ....x 0000.0000000000000000000000000000 BEB0.FFFFFFFFFFFFFFFFFFFFFFFFE7FF soft: BEB0.FFFFFFFFFFFFFFFFFFFFFFFFE7FF ..... syst: 3EB0.FFFFFFFFFFFF0000000000000000 ....x C016.0000000000002000000002000000 1F41.FFBFFFFFFFFFFFFFFFFFFFFFFF00 soft: C016.0000000000002000000002000000 ....x syst: C016.000000000000FFFFFFFFFFFFE7FF ....x BF7E.FFFFFFFFFFFFFFFFFFFFDFFDFFFF 0000.0000000000000000000000000000 soft: BF7E.FFFFFFFFFFFFFFFFFFFFDFFDFFFF ..... syst: 3F7E.FFFFFFFFFFFFFFFFFFFFFFFFFF00 ....x BFFB.FFFFFFFFFFFFFC40000000000000 0001.FFFFFFFFFFFFFFFFFFFFFFFDFC00 soft: BFFB.FFFFFFFFFFFFFC40000000000000 ....x syst: 3FFB.FFFFFFFFFFFF0000000000000000 ....x 0000.0000000000000000000000000000 0000.0000000000000000000000000000 soft: 0000.0000000000000000000000000000 ..... syst: 0000.000000000000FFFFFFFFFFFDFC00 ..... BFFB.FFC0000000000000000400000000 BF80.000000000000000000001F800000 soft: BFFB.FFC0000000000000000400000000 ....x syst: 3FFB.FFC0000000000000000000000000 ....x 0000.0000000000000000000000000000 BFBE.0000000000000100100000000000 soft: BFBE.0000000000000100100000000000 ..... syst: 3FBE.0000000000000000000000000000 ....x 4004.00000007FFFFFFFFFFFFFFFBFFFF C01E.00000000000000000000000001F7 soft: C01D.FFFFFF7FFFFFFC000000000003EE ....x syst: 401D.FFFFFF800001FC00007F7FEFFFFE ..... C01C.FFFFFF7FFFFFFFE0000000000000 0000.0000000000000000000000000001 soft: C01C.FFFFFF7FFFFFFFE0000000000000 ....x syst: C01C.FFFFFF7FFFFF00000000000001F7 ....x Errors found in float128_add, rounding to_zero: Errors found in float128_add, rounding down: Errors found in float128_add, rounding up: Errors found in float128_sub, rounding nearest_even: Errors found in float128_sub, rounding to_zero: Errors found in float128_sub, rounding down: Errors found in float128_sub, rounding up: Errors found in float128_mul, rounding nearest_even: C06C.FFFFDFFFFFFFFFFFF00000000000 C0DC.FFFFFFFFFFFFFFFFFFFFFF800020 soft: 414A.FFFFDFFFFFFFFFFFEFFFFF800028 ....x syst: 414A.FFFFDFFFFFFFFFFFF00000FFE000 ....x 0000.0000000000000000000000000000 43FE.0800000000001000000000000000 soft: 0000.0000000000000000000000000000 ..... syst: 83D0.07FFFFFFFF7C0021000000000000 ..... 3BFF.7E97EDA7689F2B4952393B680C8B 374C.949D21B83C86FE11B4148F1FEAFD soft: 334D.2E594C4EEF088CD5E6EFE7B355C6 ....x syst: 334D.2E594C4EEF07D9C39F54D086FD89 ....x BFFF.FF80000000000000000100000000 0000.0000000000000000000000000000 soft: 8000.0000000000000000000000000000 ..... syst: 8000.00000000000000000001FF800000 ...ux C2C9.ED9C13ED86C05A40B5C7DC909276 C003.5288D86EA6850195EF602326C369 soft: 42CE.465FF7459E8718965538965B9141 ....x syst: C2CE.465FF7459E873264F5675B1A409E ....x 0000.0000000000000000000000000000 0000.0000000000000000000000000000 soft: 0000.0000000000000000000000000000 ..... syst: 8000.0000000000000000000000000000 ..... DC4E.FFFFFFFFFFFFFFFFE20000000000 3FFE.03FFFFFFFFFFFFFFFFFFDFFFFFFF soft: DC4E.03FFFFFFFFFFFFFFF0C3DFFFFFFF ....x syst: DC4E.03FFFFFFFFFF7DFFE20000000000 ....x 0000.0000000000000000000000000000 6673.0000001FFFFF8000000000000000 soft: 0000.0000000000000000000000000000 ..... syst: 2645.0000001FDFFEFFFB00001FE00001 ..... 4070.0000000000007E00000000000000 3F7F.FFFFFFFFFFFFFFFFFFFFFFFFE008 soft: 3FF1.0000000000007DFFFFFFFFFFF004 ....x syst: 3FF1.0000000000003EFFFFFFFFFFDF80 ..... 8001.FFFFFFFF7FFFFFFFFFFFFFFF0000 C144.3B2134230EF5D899E623DEF52865 soft: 0147.3B213422C02D8B91226668CE114B ....x syst: 8147.3B213422C02D1566A230F8840001 ....x Errors found in float128_mul, rounding to_zero: Errors found in float128_mul, rounding down: Errors found in float128_mul, rounding up: Errors found in float128_div, rounding nearest_even: FCAA.0003FFFFFFFFFFFFFFFFDFFFFFFF BFFB.0080000000000000000000004000 soft: 7CAD.FF087BC21EF087BC21EEC89B32A3 ....x syst: FCAD.FF087BC21EEE89B2AAE8AC9C37A8 ....x 0000.0000000000000000000000000000 3C00.0000000004000000000000800000 soft: 0000.0000000000000000000000000000 ..... syst: 839D.FFFFFFFFF8000000002000000000 ....x 3FE3.0000000000000008000000001000 B24F.FFFFFF0000008000000000000000 soft: CD92.0000008000000007FFE004000000 ....x syst: 4D92.0000008000003FFC001FFC8007FD ....x 4023.0000000000000000002000000100 0000.0000000000000000000000000000 soft: 7FFF.0000000000000000000000000000 .z... syst: FFFF.0000000000000000000000000000 ..o.x C070.E79797FED3CDC79B5D0D2F11EE23 BFFC.000000000001FFFFFFFFFFF00000 soft: 4073.E79797FED3C9F86C2D0F879C76C4 ....x syst: C073.E79797FED3C99C39A6D5DFB929D8 ....x 0000.0000000000000000000000000000 0000.0000000000000000000000000000 soft: 7FFF.FFFFFFFFFFFFFFFFFFFFFFFFFFFF v.... syst: FFFF.0000000000000000000000000000 .z... 401E.9D60464ED1D5220C7F3F5B8416DB BFCD.1FFFFFFFFFFFFFFFFFFFC0000000 soft: C050.6F72059B652F3AB5C671868EC03B ....x syst: 4050.6F72059B6530379F0EFFFD923381 ....x 0000.0000000000000000000000000000 C07F.0000001000100000000000000000 soft: 8000.0000000000000000000000000000 ..... syst: 8000.0000000000000000000000000000 ...ux C00E.000007FFFFFFC000000000000000 4400.FFFFFFFFFFFFFFFFFFFE80000000 soft: BC0C.000007FFFFFFC0000000C0000600 ....x syst: 3C0C.000007FFFFFF200000FFFFFFE400 ....x 8001.0007FFFFFFFFFFFFFFFFFFFFFFFF 0000.0000000000000000000000000001 soft: C06F.0007FFFFFFFFFFFFFFFFFFFFFFFF ..... syst: C02F.0008000000000001000680000000 ....x Errors found in float128_div, rounding to_zero: Errors found in float128_div, rounding down: Errors found in float128_div, rounding up: Errors found in float128_sqrt, rounding nearest_even: B6A7.FFFFFFFFFFFFFFBFFFFFFFFF7FFF soft: 7FFF.FFFFFFFFFFFFFFFFFFFFFFFFFFFF v.... syst: 3B53.6A09E667F3BCC908B2FB1366EA95 ....x 3F81.FFFFFFFFFFFFF000020000000000 soft: 3FC0.6A09E667F3BCC3608C16788B2B60 ....x syst: 7FFF.FFFFFFFFFFFFFFFFFFFFFFFFFFFF v.... 0000.0000000000000000000000000000 soft: 0000.0000000000000000000000000000 ..... syst: 1FE7.EFBDED25BF80DBB0E688CC1D095E ....x 2EEE.FFFFFFFE00000000800000000000 soft: 3776.FFFFFFFF00000000000000000000 ..... syst: 3776.FFFFFFFEFFFFFFFFBFFFFFFFE000 ....x BFFD.6B6E6BFF6AAF4ADB4B7015F42689 soft: 7FFF.FFFFFFFFFFFFFFFFFFFFFFFFFFFF v.... syst: 3FFE.3105A1F0C3146C05F9AE9CD7AE96 ....x 0000.0000000000000000000000000001 soft: 1FC8.0000000000000000000000000000 ..... syst: 7FFF.FFFFFFFFFFFFFFFFFFFFFFFFFFFF v.... 407F.FFFFFFFFFEFFFFFE000000000000 soft: 403F.6A09E667F362468E63F925B05F2A ....x syst: 403F.6A09E667F361EC0C9F641BDE7B05 ....x 4080.000007FFFFFC0000000000000000 soft: 403F.6A09EC101B484474DEA13BAA3E89 ....x syst: 403F.6A09EC101B48F97864F7410E3C1E ....x 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFF soft: 1FFF.FFFFFFFFFFFFFFFFFFFFFFFFFFFF ....x syst: 1FFF.FFFFFFFFFFFEFFFFFFFFFFFFC000 ....x 3AF7.1155D9E5AE3D960B331FD7F11D58 soft: 3D7B.088694EB5DADD504E30B7810911D ....x syst: 3D7B.088694EB5DAE084A2B23DB30D4EE ....x Errors found in float128_sqrt, rounding to_zero: Errors found in float128_sqrt, rounding down: Errors found in float128_sqrt, rounding up: Errors found in float128_eq: 0000.0000000000000000000000000000 7FFF.000000000000000000000C000000 soft: 0 v.... syst: 0 ..... BF52.FFFFFFFFFFBFFFF0000000000000 7FFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... BFFF.FEFFFFFFFF000000000000000000 7FFF.0000000000000000000000000001 soft: 0 v.... syst: 0 ..... 0000.0000000000000000000000000000 7FFF.0000000000000000000000000001 soft: 0 v.... syst: 0 ..... 0000.0000000000000000000000000000 8000.0000000000000000000000000000 soft: 1 ..... syst: 0 ..... C01E.0000100000000000000000400000 FFFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... 0000.0000000000000000000000000000 FFFF.0000000000000000000000000001 soft: 0 v.... syst: 0 ..... 0000.0000000000000000000000000001 0000.0000000000000000000000000001 soft: 1 ..... syst: 0 ..... 3F8E.0800000000000000000000080000 7FFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... 0000.0000000000000000000000000001 7FFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... BFD4.E21E216D6C4B8441000138825323 FFFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... 0000.0000000000000000000000000001 FFFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFF 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFF soft: 1 ..... syst: 0 ..... C000.C5C8E9B80F97F4977B3107298679 7FFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFF 7FFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... BFFC.E81D4E22283EDE4B371C011E8B5E FFFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... 3FFB.FFFFFFFDE0000000000000000000 FFFF.0000000000000000000000000001 soft: 0 v.... syst: 0 ..... 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFE 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFE soft: 1 ..... syst: 0 ..... FFFF.FFFFFFF7FFFFFFFFE00000000000 7FFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... Errors found in float128_le: BFFE.FFFFFFC000000000100000000000 2DA4.0000000000000003FFFFC0000000 soft: 1 ..... syst: 0 ..... C004.00000000000003FFFFFFFFFF7FFF 403D.FFFFFFFFFFFFFFFFFF0200000000 soft: 1 ..... syst: 0 ..... 0000.0000000000000000000000000000 C04A.FFFFFFFFFFFFFFFFFFFDBFFFFFFF soft: 0 ..... syst: 1 ..... BFD1.BFFFFFFFFFFFFFFFFFFFFFFF8000 4080.00000000007FF000000000000000 soft: 1 ..... syst: 0 ..... C3FF.0800000000000004000000000000 BBFF.AF7914C544B9455AE61590E9B397 soft: 1 ..... syst: 0 ..... CEB7.FFFFFFFFFFFFC000000008000000 C019.F95CFD98142698F62BF75E8F5454 soft: 1 ..... syst: 0 ..... 4003.000000000001FF80000000000000 C3FF.DFFFFFFFFFFFFFFFFFFFFBFFFFFF soft: 0 ..... syst: 1 ..... 403F.FFFFFFFFC0000000400000000000 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFE soft: 0 ..... syst: 1 ..... 3FFD.FFFFFFFFFFFFFFF8000000080000 C400.FFFFFFBFFFFFFFFFFFFFBFFFFFFF soft: 0 ..... syst: 1 ..... C070.FFFFFFFFFFFFFFFFFC0020000000 BD27.0000000000000000000007FFFFFC soft: 1 ..... syst: 0 ..... C03E.FFFFFFFFFFFFFFFFFFFFBFFFFFFE 407F.FFFFF80000000000000400000000 soft: 1 ..... syst: 0 ..... 0000.0000000000000000000000000000 BBFE.0000000020010000000000000000 soft: 0 ..... syst: 1 ..... C07E.FFFFFFFFFFFFFFFFFFFFEFF00000 BFFF.FFFFFFFF7FFFFFFFFFFFFFFBFFFF soft: 1 ..... syst: 0 ..... 3FFD.FFFFFFFFFFFFFFFFFFDFFE000000 0001.FFFFFFFFFFFFFFFFFFFFFFFFFFFF soft: 0 ..... syst: 1 ..... 38A7.0000000000000000400000000002 C002.49A5CBE57184D5273101064FA0CB soft: 0 ..... syst: 1 ..... 0000.0000000000000000000000000000 BBFF.09BA037D4AAC6418FECEC032D1BE soft: 0 ..... syst: 1 ..... 403D.48EE42CBD3B8F4DA0D4814A588CA 8002.FFFFFFFC00000000800000000000 soft: 0 ..... syst: 1 ..... 4BE8.FFFFFFFFFFE00000000000000000 0001.FFFFFFFFFFFFFFFFFFFFFFFFFFFE soft: 0 ..... syst: 1 ..... C0A3.00000000000000007FE000000000 3FFB.FF80000000000000000000000000 soft: 1 ..... syst: 0 ..... 0000.0000000000000000000000000000 BFFE.FF7FFFFFFFFFFFFFFE0000000000 soft: 0 ..... syst: 1 ..... Errors found in float128_lt: 41CE.FFFFFFE800000000000000000000 3FE0.3E716E6AB3026C337DD47DED8643 soft: 0 ..... syst: 1 ..... 0000.0000000000000000000000000000 BF38.AA3D84C3EBF4FC3B6E2FF5AD3AE7 soft: 0 ..... syst: 1 ..... 4003.5CED6F4E0FFA40312C7EEF44EA6E 0000.0000000000000000000000000000 soft: 0 ..... syst: 1 ..... DFEB.FFFFFBFFE0000000000000000000 3FFD.0000000000000400000800000000 soft: 1 ..... syst: 0 ..... 0000.0000000000000000000000000000 C070.0000000000000000003FEFFFFFFF soft: 0 ..... syst: 1 ..... B96B.FFFFFFEFFFFFFFFFFFFFFDFFFFFF 0000.0000000000000000000000000001 soft: 1 ..... syst: 0 ..... BFFF.0800000000000400000000000000 BFF3.00000007FFFFFFF8000000000000 soft: 1 ..... syst: 0 ..... 0000.0000000000000000000000000000 C00B.00000000000000000000007FFFEF soft: 0 ..... syst: 1 ..... 4070.FFFFFFFFFFFFFFF7FFFFFFFFFFEF C03E.00000000007FFFFFFFFF80000000 soft: 0 ..... syst: 1 ..... 4036.C81F9530DBFEBA675A9701F7E3DE 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFF soft: 0 ..... syst: 1 ..... C0A6.00000000000000000FFFFF800000 42E7.49D2CA1E4614FD8AED7654F0B7F2 soft: 1 ..... syst: 0 ..... B7C6.58C7AD64208A81860163CCADA399 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFE soft: 1 ..... syst: 0 ..... C01F.000FFFFFFFFFFFFFFFC000000000 3A25.FFF7FFFFFFFFC000000000000000 soft: 1 ..... syst: 0 ..... BFF8.0000000FFFFFFFFFFFFFFFFFFFFD 0001.0000000000000000000000000000 soft: 1 ..... syst: 0 ..... C002.0000003C00000000000000000000 3B9D.FFFFFFFFFFFFFFFFFFFFFEFFFFBF soft: 1 ..... syst: 0 ..... C000.FFFFFFFFFFFFFFFC000020000000 0001.0000000000000000000000000001 soft: 1 ..... syst: 0 ..... BFDC.0000800000002000000000000000 3F81.0000000000000FFFFFFFFFFF0000 soft: 1 ..... syst: 0 ..... C3FF.000000000000FFFFFFFFFF800000 400A.B3F02E070B6CF2BA390D2C19C4A0 soft: 1 ..... syst: 0 ..... C03D.B38084B367143D6595E33B2DB681 407F.0000003800000000000000000000 soft: 1 ..... syst: 0 ..... 3FFB.CDE337EC98F4AA5F832602FFDA2C BFFB.FFFFFFFFFFFFFFFFFFFFFFFF7F7F soft: 0 ..... syst: 1 ..... Errors found in float128_eq_signaling: 0000.0000000000000000000000000000 0000.0000000000000000000000000000 soft: 1 ..... syst: 0 ..... 0000.0000000000000000000000000000 7FFF.0000000000000000000000000001 soft: 0 v.... syst: 0 ..... 0000.0000000000000000000000000000 8000.0000000000000000000000000000 soft: 1 ..... syst: 0 ..... BFFC.7333D0F0C60C5591C490788DF424 FFFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... 0000.0000000000000000000000000000 FFFF.0000000000000000000000000001 soft: 0 v.... syst: 0 ..... 0000.0000000000000000000000000001 0000.0000000000000000000000000001 soft: 1 ..... syst: 0 ..... 4023.8FC1E7E3878591D63F47F92D0CDB 7FFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... 0000.0000000000000000000000000001 7FFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... B265.007FFFFFFFFFFFFFFFFFFFFFFDFF FFFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... 0000.0000000000000000000000000001 FFFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... 3F63.7C00000000000000000000000000 FFFF.0000000000000000000000000001 soft: 0 v.... syst: 0 ..... 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFF 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFF soft: 1 ..... syst: 0 ..... 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFF 7FFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... C400.FFFFA00000000000000000000000 FFFF.00000000000000000FE000000000 soft: 0 v.... syst: 0 ..... FFFF.0000000000000000003FF0000000 3B0F.00000000000000FFFFFFFFFFFFC0 soft: 0 v.... syst: 0 ..... 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFE 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFE soft: 1 ..... syst: 0 ..... 403F.BB150A05EB2178E01560C4688C5C 7FFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFE 7FFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... BE51.0000000000000000000200200000 FFFF.0000000000000000000000000000 soft: 0 ..... syst: 0 v.... Errors found in float128_le_quiet: C03F.FFFFFFFFFFEFFFFFFFF000000000 404B.FFFFFFFFFFFFFFFEFFFFFFFFF7FF soft: 1 ..... syst: 0 ..... B867.00FFFFFFFC000000000000000000 471F.5BCF08795420E5194F5FDA6A152E soft: 1 ..... syst: 0 ..... 0000.0000000000000000000000000000 0000.0000000000000000000000000000 soft: 1 ..... syst: 0 ..... 0000.0000000000000000000000000000 BC1E.0000020000000000000000400000 soft: 0 ..... syst: 1 ..... 0000.0000000000000000000000000000 BF7E.06096645EEDE21E4901D106F095F soft: 0 ..... syst: 1 ..... 4008.0000000002000000000001000000 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFF soft: 0 ..... syst: 1 ..... CD4E.FFFFFFFFF0000000000000200000 C3FE.3E7FE203C4A8DA9F6C2CF3AF4009 soft: 1 ..... syst: 0 ..... FFFD.FFFFFFFFFFFFFFFFFFFFE0000200 13CB.FFFFFFFFFFF7FFFFFFFFFFFFFFBF soft: 1 ..... syst: 0 ..... 0000.0000000000000000000000000000 C00E.4B8C2D2C25FF18BB25C7D6A6BF8F soft: 0 ..... syst: 1 ..... 401C.FFFFFFFFFBE00000000000000000 FFFE.0010000004000000000000000000 soft: 0 ..... syst: 1 ..... 407F.0000082000000000000000000000 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFE soft: 0 ..... syst: 1 ..... C01F.FFFFFFFFFFFFFFFFFFDFFFE00000 C017.0000000000090000000000000000 soft: 1 ..... syst: 0 ..... C070.9428B15A971F54B297E53506CEA7 C003.000000000FFFFFFFFFFFFFFFFFFD soft: 1 ..... syst: 0 ..... 4005.FFFF800000000000000000000008 0001.0000000000000000000000000000 soft: 0 ..... syst: 1 ..... 3FFE.FFFFFFFFFFFBFFFFFFFFFFFFFBFF C03F.FFFFFFFFFFFFFFFFFFFFFFFEBFFF soft: 0 ..... syst: 1 ..... 0000.0000000000000000000000000000 C03C.FFFFFFFFFFFFFFFFFFFEFFFFEFFF soft: 0 ..... syst: 1 ..... C001.EFFFFFFFFFFFFFFFFFFFEFFFFFFF 0001.0000000000000000000000000001 soft: 1 ..... syst: 0 ..... C000.0000800000000000800000000000 B047.0007FFFFFFFFFFFFF80000000000 soft: 1 ..... syst: 0 ..... 400A.1FFFFFFFFFFFFFFFFFFFFFFFFFE0 0001.FFFFFFFFFFFFFFFFFFFFFFFFFFFF soft: 0 ..... syst: 1 ..... C2AD.788271EF80926974DE41DB37DF7E 43BF.FFFFFFFF80000000000000001000 soft: 1 ..... syst: 0 ..... Errors found in float128_lt_quiet: 0000.0000000000000000000000000000 BFFB.FFFFFFFFFE000000001000000000 soft: 0 ..... syst: 1 ..... 3FFD.0010000000000000100000000000 C064.7FFFFFFFFFFFFFFFFFFFFF000000 soft: 0 ..... syst: 1 ..... C016.A0E1B208FF51E84B913884DCF266 401F.AEFB2FF2FFF8085BC51986151F6A soft: 1 ..... syst: 0 ..... C137.993525BED5350E0CF3440574F3DE BC5C.FFBFFFFFFFFFFFC0000000000000 soft: 1 ..... syst: 0 ..... 0000.0000000000000000000000000000 BEC7.00FFFFFFFFFFFFFFFFE000000000 soft: 0 ..... syst: 1 ..... 3F8E.0000000000000000000FFFFFFFBF 2D5D.00000000000000000007FFBFFFFF soft: 0 ..... syst: 1 ..... C3FF.FFFFFFFFFFFFFFFFFFFFFFFFFFFF 0000.0000000000000000000000000001 soft: 1 ..... syst: 0 ..... BDF3.FF7FFFFFFFFFFFFFFFFFFFFFFFF7 4002.0000000000000FFF000000000000 soft: 1 ..... syst: 0 ..... 0000.0000000000000000000000000000 0000.0000000000000000000000000001 soft: 1 ..... syst: 0 ..... C003.8000000000000000000000000400 C002.FFFFEFFFFFFFFFFFFFFFFDFFFFFF soft: 1 ..... syst: 0 ..... 3996.1134B7B464B394AB65458DCE31D4 BF7E.435149F0BF99901BFD201C821228 soft: 0 ..... syst: 1 ..... BFFB.000000000000000000C000000000 0000.FFFFFFFFFFFFFFFFFFFFFFFFFFFE soft: 1 ..... syst: 0 ..... 3FC4.0000000000000400800000000000 C002.000000007FFFF800000000000000 soft: 0 ..... syst: 1 ..... 403C.D1502E96992AA980AC44903FB4CE C080.FFFFFFFFFFFFFFFFFFEFFFFFC000 soft: 0 ..... syst: 1 ..... 0000.0000000000000000000000000000 BFA2.94B1FC28BD21B9DB9D94C4BDA512 soft: 0 ..... syst: 1 ..... 0000.0000000000000000000000000000 BF8E.2000000000000000000000002000 soft: 0 ..... syst: 1 ..... 4001.6A01D89A27E2FE7E843C6C2ECB89 0001.0000000000000000000000000001 soft: 0 ..... syst: 1 ..... 401D.FFFFFFFFFC000000000000000020 C03C.0400008000000000000000000000 soft: 0 ..... syst: 1 ..... C03F.7423B6BDE1D7F3C27BE60320E845 0001.FFFFFFFFFFFFFFFFFFFFFFFFFFFE soft: 1 ..... syst: 0 ..... C014.FFFFFFFFFFFFFEFFFFFFEFFFFFFF 4001.FFFFFFFFFFBFFFFFFFF000000000 soft: 1 ..... syst: 0 ..... -- Peter Jeremy
Author: marius Date: Sun Mar 21 13:18:08 2010 New Revision: 205410 URL: http://svn.freebsd.org/changeset/base/205410 Log: Avoid aliasing which leads to incorrect results when compiling with the default strict aliasing rules. PR: 144900 Submitted by: Peter Jeremy MFC after: 3 days Modified: head/lib/libc/sparc64/fpu/fpu_explode.c Modified: head/lib/libc/sparc64/fpu/fpu_explode.c ============================================================================== --- head/lib/libc/sparc64/fpu/fpu_explode.c Sun Mar 21 13:09:54 2010 (r205409) +++ head/lib/libc/sparc64/fpu/fpu_explode.c Sun Mar 21 13:18:08 2010 (r205410) @@ -139,9 +139,9 @@ __fpu_xtof(fp, i) * a signed or unsigned entity. */ if (fp->fp_sign && (int64_t)i < 0) - *((int64_t*)fp->fp_mant) = -i; + *((int64_t *)fp->fp_mant) = -i; else - *((int64_t*)fp->fp_mant) = i; + *((int64_t *)fp->fp_mant) = i; fp->fp_mant[2] = 0; fp->fp_mant[3] = 0; __fpu_norm(fp); @@ -262,14 +262,12 @@ __fpu_explode(fe, fp, type, reg) struct fpn *fp; int type, reg; { - u_int32_t s, *sp; - u_int64_t l[2]; - void *vl = l; + u_int64_t l0, l1; + u_int32_t s; if (type == FTYPE_LNG || type == FTYPE_DBL || type == FTYPE_EXT) { - l[0] = __fpu_getreg64(reg & ~1); - sp = vl; - fp->fp_sign = sp[0] >> 31; + l0 = __fpu_getreg64(reg & ~1); + fp->fp_sign = l0 >> 63; } else { s = __fpu_getreg(reg); fp->fp_sign = s >> 31; @@ -277,7 +275,7 @@ __fpu_explode(fe, fp, type, reg) fp->fp_sticky = 0; switch (type) { case FTYPE_LNG: - s = __fpu_xtof(fp, l[0]); + s = __fpu_xtof(fp, l0); break; case FTYPE_INT: @@ -289,12 +287,13 @@ __fpu_explode(fe, fp, type, reg) break; case FTYPE_DBL: - s = __fpu_dtof(fp, sp[0], sp[1]); + s = __fpu_dtof(fp, l0 >> 32, l0 & 0xffffffff); break; case FTYPE_EXT: - l[1] = __fpu_getreg64((reg & ~1) + 2); - s = __fpu_qtof(fp, sp[0], sp[1], sp[2], sp[3]); + l1 = __fpu_getreg64((reg & ~1) + 2); + s = __fpu_qtof(fp, l0 >> 32, l0 & 0xffffffff, l1 >> 32, + l1 & 0xffffffff); break; default: _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
On Sun, Mar 21, 2010 at 11:28:32AM +1100, Peter Jeremy wrote: > On 2010-Mar-20 21:49:41 +0100, Marius Strobl <marius@alchemy.franken.de> wrote: > >On Sat, Mar 20, 2010 at 08:11:20PM +1100, Peter Jeremy wrote: > >> - Parts of the emulator code must be compiled with no-strict-aliasing > >> specified to function correctly. CFLAGS is updated to include the > >> relevant gcc option. (This will add -fno-strict-aliasing to all of > >> libc - which is excessive but I don't believe it's possible to compile > >> only part of libc that way). > > > >Could you please elaborate on what exactly breaks when compiling > >with strict aliasing rules? I think there actually is a way to > >limit -no-strict-aliasing to the emulator part but I'd like to > >understand what's going on and make sure there's no way it can > >be solved by the code affected before turning it on. > > OK. I spent some time looking at fpu_explode.c and came up with the > attached patch which seems to remove the requirement for > no-strict-aliasing (and I think the code looks cleaner as well). Thanks; I've decided to go that route instead of adding -fno-strict-aliasing as the code seems to be otherwise fine when it comes to strict aliasing rules, i.e. the type-punning used in fpu_qp.c is safe according to the GCC documentation. Marius
Author: marius Date: Tue Mar 30 19:03:26 2010 New Revision: 205890 URL: http://svn.freebsd.org/changeset/base/205890 Log: MFC: r205394 Ensure that __fpu_ftox() both returns the high bits and res[1] contains the low bits also in the default case. PR: 144900 Obtained from: OpenBSD Modified: stable/8/lib/libc/sparc64/fpu/fpu_implode.c Directory Properties: stable/8/lib/libc/ (props changed) stable/8/lib/libc/stdtime/ (props changed) Modified: stable/8/lib/libc/sparc64/fpu/fpu_implode.c ============================================================================== --- stable/8/lib/libc/sparc64/fpu/fpu_implode.c Tue Mar 30 18:58:10 2010 (r205889) +++ stable/8/lib/libc/sparc64/fpu/fpu_implode.c Tue Mar 30 19:03:26 2010 (r205890) @@ -248,8 +248,8 @@ __fpu_ftox(fe, fp, res) sign = fp->fp_sign; switch (fp->fp_class) { case FPC_ZERO: - res[1] = 0; - return (0); + i = 0; + goto done; case FPC_NUM: /* @@ -273,15 +273,17 @@ __fpu_ftox(fe, fp, res) break; if (sign) i = -i; - res[1] = (int)i; - return (i >> 32); + goto done; default: /* Inf, qNaN, sNaN */ break; } /* overflow: replace any inexact exception with invalid */ fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; - return (0x7fffffffffffffffLL + sign); + i = 0x7fffffffffffffffLL + sign; +done: + res[1] = i & 0xffffffff; + return (i >> 32); } /* _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Tue Mar 30 19:03:27 2010 New Revision: 205891 URL: http://svn.freebsd.org/changeset/base/205891 Log: MFC: r205394 Ensure that __fpu_ftox() both returns the high bits and res[1] contains the low bits also in the default case. PR: 144900 Obtained from: OpenBSD Modified: stable/7/lib/libc/sparc64/fpu/fpu_implode.c Directory Properties: stable/7/lib/libc/ (props changed) stable/7/lib/libc/stdtime/ (props changed) Modified: stable/7/lib/libc/sparc64/fpu/fpu_implode.c ============================================================================== --- stable/7/lib/libc/sparc64/fpu/fpu_implode.c Tue Mar 30 19:03:26 2010 (r205890) +++ stable/7/lib/libc/sparc64/fpu/fpu_implode.c Tue Mar 30 19:03:27 2010 (r205891) @@ -248,8 +248,8 @@ __fpu_ftox(fe, fp, res) sign = fp->fp_sign; switch (fp->fp_class) { case FPC_ZERO: - res[1] = 0; - return (0); + i = 0; + goto done; case FPC_NUM: /* @@ -273,15 +273,17 @@ __fpu_ftox(fe, fp, res) break; if (sign) i = -i; - res[1] = (int)i; - return (i >> 32); + goto done; default: /* Inf, qNaN, sNaN */ break; } /* overflow: replace any inexact exception with invalid */ fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; - return (0x7fffffffffffffffLL + sign); + i = 0x7fffffffffffffffLL + sign; +done: + res[1] = i & 0xffffffff; + return (i >> 32); } /* _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Tue Mar 30 19:03:29 2010 New Revision: 205892 URL: http://svn.freebsd.org/changeset/base/205892 Log: MFC: r205394 Ensure that __fpu_ftox() both returns the high bits and res[1] contains the low bits also in the default case. PR:i 144900 Obtained from: OpenBSD Modified: stable/6/lib/libc/sparc64/fpu/fpu_implode.c Directory Properties: stable/6/lib/libc/ (props changed) Modified: stable/6/lib/libc/sparc64/fpu/fpu_implode.c ============================================================================== --- stable/6/lib/libc/sparc64/fpu/fpu_implode.c Tue Mar 30 19:03:27 2010 (r205891) +++ stable/6/lib/libc/sparc64/fpu/fpu_implode.c Tue Mar 30 19:03:29 2010 (r205892) @@ -252,8 +252,8 @@ __fpu_ftox(fe, fp, res) sign = fp->fp_sign; switch (fp->fp_class) { case FPC_ZERO: - res[1] = 0; - return (0); + i = 0; + goto done; case FPC_NUM: /* @@ -277,15 +277,17 @@ __fpu_ftox(fe, fp, res) break; if (sign) i = -i; - res[1] = (int)i; - return (i >> 32); + goto done; default: /* Inf, qNaN, sNaN */ break; } /* overflow: replace any inexact exception with invalid */ fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; - return (0x7fffffffffffffffLL + sign); + i = 0x7fffffffffffffffLL + sign; +done: + res[1] = i & 0xffffffff; + return (i >> 32); } /* _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Tue Mar 30 19:05:08 2010 New Revision: 205893 URL: http://svn.freebsd.org/changeset/base/205893 Log: MFC: r205395 FPU_DEBUG requires <stdio.h>. PR: 144900 Submitted by: Peter Jeremy Modified: stable/8/lib/libc/sparc64/fpu/fpu.c stable/8/lib/libc/sparc64/fpu/fpu_explode.c stable/8/lib/libc/sparc64/fpu/fpu_implode.c Directory Properties: stable/8/lib/libc/ (props changed) stable/8/lib/libc/stdtime/ (props changed) Modified: stable/8/lib/libc/sparc64/fpu/fpu.c ============================================================================== --- stable/8/lib/libc/sparc64/fpu/fpu.c Tue Mar 30 19:03:29 2010 (r205892) +++ stable/8/lib/libc/sparc64/fpu/fpu.c Tue Mar 30 19:05:08 2010 (r205893) @@ -69,9 +69,12 @@ __FBSDID("$FreeBSD$"); #include "namespace.h" #include <errno.h> -#include <unistd.h> #include <signal.h> +#ifdef FPU_DEBUG +#include <stdio.h> +#endif #include <stdlib.h> +#include <unistd.h> #include "un-namespace.h" #include "libc_private.h" Modified: stable/8/lib/libc/sparc64/fpu/fpu_explode.c ============================================================================== --- stable/8/lib/libc/sparc64/fpu/fpu_explode.c Tue Mar 30 19:03:29 2010 (r205892) +++ stable/8/lib/libc/sparc64/fpu/fpu_explode.c Tue Mar 30 19:05:08 2010 (r205893) @@ -49,6 +49,10 @@ __FBSDID("$FreeBSD$"); #include <sys/param.h> +#ifdef FPU_DEBUG +#include <stdio.h> +#endif + #include <machine/frame.h> #include <machine/fp.h> #include <machine/fsr.h> Modified: stable/8/lib/libc/sparc64/fpu/fpu_implode.c ============================================================================== --- stable/8/lib/libc/sparc64/fpu/fpu_implode.c Tue Mar 30 19:03:29 2010 (r205892) +++ stable/8/lib/libc/sparc64/fpu/fpu_implode.c Tue Mar 30 19:05:08 2010 (r205893) @@ -49,6 +49,10 @@ __FBSDID("$FreeBSD$"); #include <sys/param.h> +#ifdef FPU_DEBUG +#include <stdio.h> +#endif + #include <machine/frame.h> #include <machine/fp.h> #include <machine/fsr.h> _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Tue Mar 30 19:05:11 2010 New Revision: 205894 URL: http://svn.freebsd.org/changeset/base/205894 Log: MFC: r205395 FPU_DEBUG requires <stdio.h>. PR: 144900 Submitted by: Peter Jeremy Modified: stable/7/lib/libc/sparc64/fpu/fpu.c stable/7/lib/libc/sparc64/fpu/fpu_explode.c stable/7/lib/libc/sparc64/fpu/fpu_implode.c Directory Properties: stable/7/lib/libc/ (props changed) stable/7/lib/libc/stdtime/ (props changed) Modified: stable/7/lib/libc/sparc64/fpu/fpu.c ============================================================================== --- stable/7/lib/libc/sparc64/fpu/fpu.c Tue Mar 30 19:05:08 2010 (r205893) +++ stable/7/lib/libc/sparc64/fpu/fpu.c Tue Mar 30 19:05:11 2010 (r205894) @@ -69,9 +69,12 @@ __FBSDID("$FreeBSD$"); #include "namespace.h" #include <errno.h> -#include <unistd.h> #include <signal.h> +#ifdef FPU_DEBUG +#include <stdio.h> +#endif #include <stdlib.h> +#include <unistd.h> #include "un-namespace.h" #include "libc_private.h" Modified: stable/7/lib/libc/sparc64/fpu/fpu_explode.c ============================================================================== --- stable/7/lib/libc/sparc64/fpu/fpu_explode.c Tue Mar 30 19:05:08 2010 (r205893) +++ stable/7/lib/libc/sparc64/fpu/fpu_explode.c Tue Mar 30 19:05:11 2010 (r205894) @@ -49,6 +49,10 @@ __FBSDID("$FreeBSD$"); #include <sys/param.h> +#ifdef FPU_DEBUG +#include <stdio.h> +#endif + #include <machine/frame.h> #include <machine/fp.h> #include <machine/fsr.h> Modified: stable/7/lib/libc/sparc64/fpu/fpu_implode.c ============================================================================== --- stable/7/lib/libc/sparc64/fpu/fpu_implode.c Tue Mar 30 19:05:08 2010 (r205893) +++ stable/7/lib/libc/sparc64/fpu/fpu_implode.c Tue Mar 30 19:05:11 2010 (r205894) @@ -49,6 +49,10 @@ __FBSDID("$FreeBSD$"); #include <sys/param.h> +#ifdef FPU_DEBUG +#include <stdio.h> +#endif + #include <machine/frame.h> #include <machine/fp.h> #include <machine/fsr.h> _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Tue Mar 30 19:05:20 2010 New Revision: 205895 URL: http://svn.freebsd.org/changeset/base/205895 Log: MFC: r205395 FPU_DEBUG requires <stdio.h>. PR: 144900 Submitted by: Peter Jeremy Modified: stable/6/lib/libc/sparc64/fpu/fpu.c stable/6/lib/libc/sparc64/fpu/fpu_explode.c stable/6/lib/libc/sparc64/fpu/fpu_implode.c Directory Properties: stable/6/lib/libc/ (props changed) Modified: stable/6/lib/libc/sparc64/fpu/fpu.c ============================================================================== --- stable/6/lib/libc/sparc64/fpu/fpu.c Tue Mar 30 19:05:11 2010 (r205894) +++ stable/6/lib/libc/sparc64/fpu/fpu.c Tue Mar 30 19:05:20 2010 (r205895) @@ -73,9 +73,12 @@ __FBSDID("$FreeBSD$"); #include "namespace.h" #include <errno.h> -#include <unistd.h> #include <signal.h> +#ifdef FPU_DEBUG +#include <stdio.h> +#endif #include <stdlib.h> +#include <unistd.h> #include "un-namespace.h" #include "libc_private.h" Modified: stable/6/lib/libc/sparc64/fpu/fpu_explode.c ============================================================================== --- stable/6/lib/libc/sparc64/fpu/fpu_explode.c Tue Mar 30 19:05:11 2010 (r205894) +++ stable/6/lib/libc/sparc64/fpu/fpu_explode.c Tue Mar 30 19:05:20 2010 (r205895) @@ -53,6 +53,10 @@ __FBSDID("$FreeBSD$"); #include <sys/param.h> +#ifdef FPU_DEBUG +#include <stdio.h> +#endif + #include <machine/frame.h> #include <machine/fp.h> #include <machine/fsr.h> Modified: stable/6/lib/libc/sparc64/fpu/fpu_implode.c ============================================================================== --- stable/6/lib/libc/sparc64/fpu/fpu_implode.c Tue Mar 30 19:05:11 2010 (r205894) +++ stable/6/lib/libc/sparc64/fpu/fpu_implode.c Tue Mar 30 19:05:20 2010 (r205895) @@ -53,6 +53,10 @@ __FBSDID("$FreeBSD$"); #include <sys/param.h> +#ifdef FPU_DEBUG +#include <stdio.h> +#endif + #include <machine/frame.h> #include <machine/fp.h> #include <machine/fsr.h> _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Tue Mar 30 19:06:31 2010 New Revision: 205896 URL: http://svn.freebsd.org/changeset/base/205896 Log: MFC: r205396 Division should take both arguments' signs into account when the the dividend is infinity or zero and the divisor is not the same. PR: 144900 Submitted by: Peter Jeremy Modified: stable/8/lib/libc/sparc64/fpu/fpu_div.c Directory Properties: stable/8/lib/libc/ (props changed) stable/8/lib/libc/stdtime/ (props changed) Modified: stable/8/lib/libc/sparc64/fpu/fpu_div.c ============================================================================== --- stable/8/lib/libc/sparc64/fpu/fpu_div.c Tue Mar 30 19:05:20 2010 (r205895) +++ stable/8/lib/libc/sparc64/fpu/fpu_div.c Tue Mar 30 19:06:31 2010 (r205896) @@ -167,14 +167,16 @@ __fpu_div(fe) * return it. Otherwise we have the following cases: * * Inf / Inf = NaN, plus NV exception - * Inf / num = Inf [i.e., return x] - * Inf / 0 = Inf [i.e., return x] - * 0 / Inf = 0 [i.e., return x] - * 0 / num = 0 [i.e., return x] + * Inf / num = Inf [i.e., return x #] + * Inf / 0 = Inf [i.e., return x #] + * 0 / Inf = 0 [i.e., return x #] + * 0 / num = 0 [i.e., return x #] * 0 / 0 = NaN, plus NV exception - * num / Inf = 0 + * num / Inf = 0 # * num / num = num (do the divide) - * num / 0 = Inf, plus DZ exception + * num / 0 = Inf #, plus DZ exception + * + * # Sign of result is XOR of operand signs. */ if (ISNAN(x) || ISNAN(y)) { ORDER(x, y); @@ -183,10 +185,10 @@ __fpu_div(fe) if (ISINF(x) || ISZERO(x)) { if (x->fp_class == y->fp_class) return (__fpu_newnan(fe)); + x->fp_sign ^= y->fp_sign; return (x); } - /* all results at this point use XOR of operand signs */ x->fp_sign ^= y->fp_sign; if (ISINF(y)) { x->fp_class = FPC_ZERO; _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Tue Mar 30 19:06:33 2010 New Revision: 205897 URL: http://svn.freebsd.org/changeset/base/205897 Log: MFC: r205396 Division should take both arguments' signs into account when the the dividend is infinity or zero and the divisor is not the same. PR: 144900 Submitted by: Peter Jeremy Modified: stable/7/lib/libc/sparc64/fpu/fpu_div.c Directory Properties: stable/7/lib/libc/ (props changed) stable/7/lib/libc/stdtime/ (props changed) Modified: stable/7/lib/libc/sparc64/fpu/fpu_div.c ============================================================================== --- stable/7/lib/libc/sparc64/fpu/fpu_div.c Tue Mar 30 19:06:31 2010 (r205896) +++ stable/7/lib/libc/sparc64/fpu/fpu_div.c Tue Mar 30 19:06:33 2010 (r205897) @@ -167,14 +167,16 @@ __fpu_div(fe) * return it. Otherwise we have the following cases: * * Inf / Inf = NaN, plus NV exception - * Inf / num = Inf [i.e., return x] - * Inf / 0 = Inf [i.e., return x] - * 0 / Inf = 0 [i.e., return x] - * 0 / num = 0 [i.e., return x] + * Inf / num = Inf [i.e., return x #] + * Inf / 0 = Inf [i.e., return x #] + * 0 / Inf = 0 [i.e., return x #] + * 0 / num = 0 [i.e., return x #] * 0 / 0 = NaN, plus NV exception - * num / Inf = 0 + * num / Inf = 0 # * num / num = num (do the divide) - * num / 0 = Inf, plus DZ exception + * num / 0 = Inf #, plus DZ exception + * + * # Sign of result is XOR of operand signs. */ if (ISNAN(x) || ISNAN(y)) { ORDER(x, y); @@ -183,10 +185,10 @@ __fpu_div(fe) if (ISINF(x) || ISZERO(x)) { if (x->fp_class == y->fp_class) return (__fpu_newnan(fe)); + x->fp_sign ^= y->fp_sign; return (x); } - /* all results at this point use XOR of operand signs */ x->fp_sign ^= y->fp_sign; if (ISINF(y)) { x->fp_class = FPC_ZERO; _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Tue Mar 30 19:06:37 2010 New Revision: 205898 URL: http://svn.freebsd.org/changeset/base/205898 Log: MFC: r205396 Division should take both arguments' signs into account when the the dividend is infinity or zero and the divisor is not the same. PR: 144900 Submitted by: Peter Jeremy Modified: stable/6/lib/libc/sparc64/fpu/fpu_div.c Directory Properties: stable/6/lib/libc/ (props changed) Modified: stable/6/lib/libc/sparc64/fpu/fpu_div.c ============================================================================== --- stable/6/lib/libc/sparc64/fpu/fpu_div.c Tue Mar 30 19:06:33 2010 (r205897) +++ stable/6/lib/libc/sparc64/fpu/fpu_div.c Tue Mar 30 19:06:37 2010 (r205898) @@ -171,14 +171,16 @@ __fpu_div(fe) * return it. Otherwise we have the following cases: * * Inf / Inf = NaN, plus NV exception - * Inf / num = Inf [i.e., return x] - * Inf / 0 = Inf [i.e., return x] - * 0 / Inf = 0 [i.e., return x] - * 0 / num = 0 [i.e., return x] + * Inf / num = Inf [i.e., return x #] + * Inf / 0 = Inf [i.e., return x #] + * 0 / Inf = 0 [i.e., return x #] + * 0 / num = 0 [i.e., return x #] * 0 / 0 = NaN, plus NV exception - * num / Inf = 0 + * num / Inf = 0 # * num / num = num (do the divide) - * num / 0 = Inf, plus DZ exception + * num / 0 = Inf #, plus DZ exception + * + * # Sign of result is XOR of operand signs. */ if (ISNAN(x) || ISNAN(y)) { ORDER(x, y); @@ -187,10 +189,10 @@ __fpu_div(fe) if (ISINF(x) || ISZERO(x)) { if (x->fp_class == y->fp_class) return (__fpu_newnan(fe)); + x->fp_sign ^= y->fp_sign; return (x); } - /* all results at this point use XOR of operand signs */ x->fp_sign ^= y->fp_sign; if (ISINF(y)) { x->fp_class = FPC_ZERO; _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Tue Mar 30 19:08:01 2010 New Revision: 205901 URL: http://svn.freebsd.org/changeset/base/205901 Log: MFC: r205397 - While SPARC V9 allows tininess to be detected either before or after rounding (impl. dep. #55), the SPARC JPS1 responsible for SPARC64 and UltraSPARC processors defines that in all cases tinyness is detected before rounding, therefore rounding up to the smallest normalised number should set the underflow flag. - If an infinite result is rounded down, the result should have an exponent 1 less than the value for infinity. PR: 144900 Submitted by: Peter Jeremy Modified: stable/7/lib/libc/sparc64/fpu/fpu_implode.c Directory Properties: stable/7/lib/libc/ (props changed) stable/7/lib/libc/stdtime/ (props changed) Modified: stable/7/lib/libc/sparc64/fpu/fpu_implode.c ============================================================================== --- stable/7/lib/libc/sparc64/fpu/fpu_implode.c Tue Mar 30 19:07:41 2010 (r205900) +++ stable/7/lib/libc/sparc64/fpu/fpu_implode.c Tue Mar 30 19:08:01 2010 (r205901) @@ -329,8 +329,9 @@ __fpu_ftos(fe, fp) * right to introduce leading zeroes. Rounding then acts * differently for normals and subnormals: the largest subnormal * may round to the smallest normal (1.0 x 2^minexp), or may - * remain subnormal. In the latter case, signal an underflow - * if the result was inexact or if underflow traps are enabled. + * remain subnormal. A number that is subnormal before rounding + * will signal an underflow if the result is inexact or if underflow + * traps are enabled. * * Rounding a normal, on the other hand, always produces another * normal (although either way the result might be too big for @@ -345,8 +346,10 @@ __fpu_ftos(fe, fp) if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ (void) __fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); - if (fpround(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) + if (fpround(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) { + fe->fe_cx |= FSR_UF; return (sign | SNG_EXP(1) | 0); + } if ((fe->fe_cx & FSR_NX) || (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) fe->fe_cx |= FSR_UF; @@ -407,6 +410,7 @@ zero: res[1] = 0; if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { (void) __fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); if (fpround(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { + fe->fe_cx |= FSR_UF; res[1] = 0; return (sign | DBL_EXP(1) | 0); } @@ -426,7 +430,7 @@ zero: res[1] = 0; return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); } res[1] = ~0; - return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); + return (sign | DBL_EXP(DBL_EXP_INFNAN - 1) | DBL_MASK); } done: res[1] = fp->fp_mant[3]; @@ -468,6 +472,7 @@ zero: res[1] = res[2] = res[3] = 0; if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) { (void) __fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp); if (fpround(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) { + fe->fe_cx |= FSR_UF; res[1] = res[2] = res[3] = 0; return (sign | EXT_EXP(1) | 0); } @@ -487,7 +492,7 @@ zero: res[1] = res[2] = res[3] = 0; return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0); } res[1] = res[2] = res[3] = ~0; - return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK); + return (sign | EXT_EXP(EXT_EXP_INFNAN - 1) | EXT_MASK); } done: res[1] = fp->fp_mant[1]; _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Tue Mar 30 19:08:02 2010 New Revision: 205902 URL: http://svn.freebsd.org/changeset/base/205902 Log: MFC: r205397 - While SPARC V9 allows tininess to be detected either before or after rounding (impl. dep. #55), the SPARC JPS1 responsible for SPARC64 and UltraSPARC processors defines that in all cases tinyness is detected before rounding, therefore rounding up to the smallest normalised number should set the underflow flag. - If an infinite result is rounded down, the result should have an exponent 1 less than the value for infinity. PR: 144900 Submitted by: Peter Jeremy Modified: stable/8/lib/libc/sparc64/fpu/fpu_implode.c Directory Properties: stable/8/lib/libc/ (props changed) stable/8/lib/libc/stdtime/ (props changed) Modified: stable/8/lib/libc/sparc64/fpu/fpu_implode.c ============================================================================== --- stable/8/lib/libc/sparc64/fpu/fpu_implode.c Tue Mar 30 19:08:01 2010 (r205901) +++ stable/8/lib/libc/sparc64/fpu/fpu_implode.c Tue Mar 30 19:08:02 2010 (r205902) @@ -329,8 +329,9 @@ __fpu_ftos(fe, fp) * right to introduce leading zeroes. Rounding then acts * differently for normals and subnormals: the largest subnormal * may round to the smallest normal (1.0 x 2^minexp), or may - * remain subnormal. In the latter case, signal an underflow - * if the result was inexact or if underflow traps are enabled. + * remain subnormal. A number that is subnormal before rounding + * will signal an underflow if the result is inexact or if underflow + * traps are enabled. * * Rounding a normal, on the other hand, always produces another * normal (although either way the result might be too big for @@ -345,8 +346,10 @@ __fpu_ftos(fe, fp) if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ (void) __fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); - if (fpround(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) + if (fpround(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) { + fe->fe_cx |= FSR_UF; return (sign | SNG_EXP(1) | 0); + } if ((fe->fe_cx & FSR_NX) || (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) fe->fe_cx |= FSR_UF; @@ -407,6 +410,7 @@ zero: res[1] = 0; if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { (void) __fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); if (fpround(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { + fe->fe_cx |= FSR_UF; res[1] = 0; return (sign | DBL_EXP(1) | 0); } @@ -426,7 +430,7 @@ zero: res[1] = 0; return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); } res[1] = ~0; - return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); + return (sign | DBL_EXP(DBL_EXP_INFNAN - 1) | DBL_MASK); } done: res[1] = fp->fp_mant[3]; @@ -468,6 +472,7 @@ zero: res[1] = res[2] = res[3] = 0; if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) { (void) __fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp); if (fpround(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) { + fe->fe_cx |= FSR_UF; res[1] = res[2] = res[3] = 0; return (sign | EXT_EXP(1) | 0); } @@ -487,7 +492,7 @@ zero: res[1] = res[2] = res[3] = 0; return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0); } res[1] = res[2] = res[3] = ~0; - return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK); + return (sign | EXT_EXP(EXT_EXP_INFNAN - 1) | EXT_MASK); } done: res[1] = fp->fp_mant[1]; _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Tue Mar 30 19:08:05 2010 New Revision: 205903 URL: http://svn.freebsd.org/changeset/base/205903 Log: MFC: r205397 - While SPARC V9 allows tininess to be detected either before or after rounding (impl. dep. #55), the SPARC JPS1 responsible for SPARC64 and UltraSPARC processors defines that in all cases tinyness is detected before rounding, therefore rounding up to the smallest normalised number should set the underflow flag. - If an infinite result is rounded down, the result should have an exponent 1 less than the value for infinity. PR: 144900 Submitted by: Peter Jeremy Modified: stable/6/lib/libc/sparc64/fpu/fpu_implode.c Directory Properties: stable/6/lib/libc/ (props changed) Modified: stable/6/lib/libc/sparc64/fpu/fpu_implode.c ============================================================================== --- stable/6/lib/libc/sparc64/fpu/fpu_implode.c Tue Mar 30 19:08:02 2010 (r205902) +++ stable/6/lib/libc/sparc64/fpu/fpu_implode.c Tue Mar 30 19:08:05 2010 (r205903) @@ -333,8 +333,9 @@ __fpu_ftos(fe, fp) * right to introduce leading zeroes. Rounding then acts * differently for normals and subnormals: the largest subnormal * may round to the smallest normal (1.0 x 2^minexp), or may - * remain subnormal. In the latter case, signal an underflow - * if the result was inexact or if underflow traps are enabled. + * remain subnormal. A number that is subnormal before rounding + * will signal an underflow if the result is inexact or if underflow + * traps are enabled. * * Rounding a normal, on the other hand, always produces another * normal (although either way the result might be too big for @@ -349,8 +350,10 @@ __fpu_ftos(fe, fp) if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ (void) __fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); - if (fpround(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) + if (fpround(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) { + fe->fe_cx |= FSR_UF; return (sign | SNG_EXP(1) | 0); + } if ((fe->fe_cx & FSR_NX) || (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) fe->fe_cx |= FSR_UF; @@ -411,6 +414,7 @@ zero: res[1] = 0; if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { (void) __fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); if (fpround(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { + fe->fe_cx |= FSR_UF; res[1] = 0; return (sign | DBL_EXP(1) | 0); } @@ -430,7 +434,7 @@ zero: res[1] = 0; return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); } res[1] = ~0; - return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); + return (sign | DBL_EXP(DBL_EXP_INFNAN - 1) | DBL_MASK); } done: res[1] = fp->fp_mant[3]; @@ -472,6 +476,7 @@ zero: res[1] = res[2] = res[3] = 0; if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) { (void) __fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp); if (fpround(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) { + fe->fe_cx |= FSR_UF; res[1] = res[2] = res[3] = 0; return (sign | EXT_EXP(1) | 0); } @@ -491,7 +496,7 @@ zero: res[1] = res[2] = res[3] = 0; return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0); } res[1] = res[2] = res[3] = ~0; - return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK); + return (sign | EXT_EXP(EXT_EXP_INFNAN - 1) | EXT_MASK); } done: res[1] = fp->fp_mant[1]; _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Tue Mar 30 19:13:37 2010 New Revision: 205905 URL: http://svn.freebsd.org/changeset/base/205905 Log: MFC: r205410 Avoid aliasing which leads to incorrect results when compiling with the default strict aliasing rules. PR: 144900 Submitted by: Peter Jeremy Modified: stable/8/lib/libc/sparc64/fpu/fpu_explode.c Directory Properties: stable/8/lib/libc/ (props changed) stable/8/lib/libc/stdtime/ (props changed) Modified: stable/8/lib/libc/sparc64/fpu/fpu_explode.c ============================================================================== --- stable/8/lib/libc/sparc64/fpu/fpu_explode.c Tue Mar 30 19:09:18 2010 (r205904) +++ stable/8/lib/libc/sparc64/fpu/fpu_explode.c Tue Mar 30 19:13:37 2010 (r205905) @@ -139,9 +139,9 @@ __fpu_xtof(fp, i) * a signed or unsigned entity. */ if (fp->fp_sign && (int64_t)i < 0) - *((int64_t*)fp->fp_mant) = -i; + *((int64_t *)fp->fp_mant) = -i; else - *((int64_t*)fp->fp_mant) = i; + *((int64_t *)fp->fp_mant) = i; fp->fp_mant[2] = 0; fp->fp_mant[3] = 0; __fpu_norm(fp); @@ -262,14 +262,12 @@ __fpu_explode(fe, fp, type, reg) struct fpn *fp; int type, reg; { - u_int32_t s, *sp; - u_int64_t l[2]; - void *vl = l; + u_int64_t l0, l1; + u_int32_t s; if (type == FTYPE_LNG || type == FTYPE_DBL || type == FTYPE_EXT) { - l[0] = __fpu_getreg64(reg & ~1); - sp = vl; - fp->fp_sign = sp[0] >> 31; + l0 = __fpu_getreg64(reg & ~1); + fp->fp_sign = l0 >> 63; } else { s = __fpu_getreg(reg); fp->fp_sign = s >> 31; @@ -277,7 +275,7 @@ __fpu_explode(fe, fp, type, reg) fp->fp_sticky = 0; switch (type) { case FTYPE_LNG: - s = __fpu_xtof(fp, l[0]); + s = __fpu_xtof(fp, l0); break; case FTYPE_INT: @@ -289,12 +287,13 @@ __fpu_explode(fe, fp, type, reg) break; case FTYPE_DBL: - s = __fpu_dtof(fp, sp[0], sp[1]); + s = __fpu_dtof(fp, l0 >> 32, l0 & 0xffffffff); break; case FTYPE_EXT: - l[1] = __fpu_getreg64((reg & ~1) + 2); - s = __fpu_qtof(fp, sp[0], sp[1], sp[2], sp[3]); + l1 = __fpu_getreg64((reg & ~1) + 2); + s = __fpu_qtof(fp, l0 >> 32, l0 & 0xffffffff, l1 >> 32, + l1 & 0xffffffff); break; default: _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Tue Mar 30 19:15:57 2010 New Revision: 205906 URL: http://svn.freebsd.org/changeset/base/205906 Log: MFC: r173859, r205410 Avoid aliasing which leads to incorrect results when compiling with the default strict aliasing rules. PR: 144900 Submitted by: Peter Jeremy Modified: stable/7/lib/libc/sparc64/fpu/fpu_explode.c Directory Properties: stable/7/lib/libc/ (props changed) stable/7/lib/libc/stdtime/ (props changed) Modified: stable/7/lib/libc/sparc64/fpu/fpu_explode.c ============================================================================== --- stable/7/lib/libc/sparc64/fpu/fpu_explode.c Tue Mar 30 19:13:37 2010 (r205905) +++ stable/7/lib/libc/sparc64/fpu/fpu_explode.c Tue Mar 30 19:15:57 2010 (r205906) @@ -139,9 +139,9 @@ __fpu_xtof(fp, i) * a signed or unsigned entity. */ if (fp->fp_sign && (int64_t)i < 0) - *((int64_t*)fp->fp_mant) = -i; + *((int64_t *)fp->fp_mant) = -i; else - *((int64_t*)fp->fp_mant) = i; + *((int64_t *)fp->fp_mant) = i; fp->fp_mant[2] = 0; fp->fp_mant[3] = 0; __fpu_norm(fp); @@ -262,13 +262,12 @@ __fpu_explode(fe, fp, type, reg) struct fpn *fp; int type, reg; { - u_int32_t s, *sp; - u_int64_t l[2]; + u_int64_t l0, l1; + u_int32_t s; if (type == FTYPE_LNG || type == FTYPE_DBL || type == FTYPE_EXT) { - l[0] = __fpu_getreg64(reg & ~1); - sp = (u_int32_t *)l; - fp->fp_sign = sp[0] >> 31; + l0 = __fpu_getreg64(reg & ~1); + fp->fp_sign = l0 >> 63; } else { s = __fpu_getreg(reg); fp->fp_sign = s >> 31; @@ -276,7 +275,7 @@ __fpu_explode(fe, fp, type, reg) fp->fp_sticky = 0; switch (type) { case FTYPE_LNG: - s = __fpu_xtof(fp, l[0]); + s = __fpu_xtof(fp, l0); break; case FTYPE_INT: @@ -288,12 +287,13 @@ __fpu_explode(fe, fp, type, reg) break; case FTYPE_DBL: - s = __fpu_dtof(fp, sp[0], sp[1]); + s = __fpu_dtof(fp, l0 >> 32, l0 & 0xffffffff); break; case FTYPE_EXT: - l[1] = __fpu_getreg64((reg & ~1) + 2); - s = __fpu_qtof(fp, sp[0], sp[1], sp[2], sp[3]); + l1 = __fpu_getreg64((reg & ~1) + 2); + s = __fpu_qtof(fp, l0 >> 32, l0 & 0xffffffff, l1 >> 32, + l1 & 0xffffffff); break; default: _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Tue Mar 30 19:16:00 2010 New Revision: 205907 URL: http://svn.freebsd.org/changeset/base/205907 Log: MFC: r173859, r205410 Avoid aliasing which leads to incorrect results when compiling with the default strict aliasing rules. PR: 144900 Submitted by: Peter Jeremy Modified: stable/6/lib/libc/sparc64/fpu/fpu_explode.c Directory Properties: stable/6/lib/libc/ (props changed) Modified: stable/6/lib/libc/sparc64/fpu/fpu_explode.c ============================================================================== --- stable/6/lib/libc/sparc64/fpu/fpu_explode.c Tue Mar 30 19:15:57 2010 (r205906) +++ stable/6/lib/libc/sparc64/fpu/fpu_explode.c Tue Mar 30 19:16:00 2010 (r205907) @@ -143,9 +143,9 @@ __fpu_xtof(fp, i) * a signed or unsigned entity. */ if (fp->fp_sign && (int64_t)i < 0) - *((int64_t*)fp->fp_mant) = -i; + *((int64_t *)fp->fp_mant) = -i; else - *((int64_t*)fp->fp_mant) = i; + *((int64_t *)fp->fp_mant) = i; fp->fp_mant[2] = 0; fp->fp_mant[3] = 0; __fpu_norm(fp); @@ -266,13 +266,12 @@ __fpu_explode(fe, fp, type, reg) struct fpn *fp; int type, reg; { - u_int32_t s, *sp; - u_int64_t l[2]; + u_int64_t l0, l1; + u_int32_t s; if (type == FTYPE_LNG || type == FTYPE_DBL || type == FTYPE_EXT) { - l[0] = __fpu_getreg64(reg & ~1); - sp = (u_int32_t *)l; - fp->fp_sign = sp[0] >> 31; + l0 = __fpu_getreg64(reg & ~1); + fp->fp_sign = l0 >> 63; } else { s = __fpu_getreg(reg); fp->fp_sign = s >> 31; @@ -280,7 +279,7 @@ __fpu_explode(fe, fp, type, reg) fp->fp_sticky = 0; switch (type) { case FTYPE_LNG: - s = __fpu_xtof(fp, l[0]); + s = __fpu_xtof(fp, l0); break; case FTYPE_INT: @@ -292,12 +291,13 @@ __fpu_explode(fe, fp, type, reg) break; case FTYPE_DBL: - s = __fpu_dtof(fp, sp[0], sp[1]); + s = __fpu_dtof(fp, l0 >> 32, l0 & 0xffffffff); break; case FTYPE_EXT: - l[1] = __fpu_getreg64((reg & ~1) + 2); - s = __fpu_qtof(fp, sp[0], sp[1], sp[2], sp[3]); + l1 = __fpu_getreg64((reg & ~1) + 2); + s = __fpu_qtof(fp, l0 >> 32, l0 & 0xffffffff, l1 >> 32, + l1 & 0xffffffff); break; default: _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Sun Apr 11 20:08:54 2010 New Revision: 206490 URL: http://svn.freebsd.org/changeset/base/206490 Log: While SPARC V9 allows tininess to be detected either before or after rounding (impl. dep. #55), the SPARC JPS1 responsible for SPARC64 and UltraSPARC processors defines that in all cases tininess is detected before rounding therefore rounding up to the smallest normalized number should set the underflow flag. This change is needed for using SoftFloat on sparc64 for reference purposes. PR: 144900 Submitted by: Peter Jeremy Modified: head/lib/libc/softfloat/softfloat-specialize Modified: head/lib/libc/softfloat/softfloat-specialize ============================================================================== --- head/lib/libc/softfloat/softfloat-specialize Sun Apr 11 19:58:01 2010 (r206489) +++ head/lib/libc/softfloat/softfloat-specialize Sun Apr 11 20:08:54 2010 (r206490) @@ -44,6 +44,9 @@ Underflow tininess-detection mode, stati #ifdef SOFTFLOAT_FOR_GCC static #endif +#ifdef __sparc64__ +int8 float_detect_tininess = float_tininess_before_rounding; +#else int8 float_detect_tininess = float_tininess_after_rounding; /* _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Sat Apr 24 12:11:41 2010 New Revision: 207151 URL: http://svn.freebsd.org/changeset/base/207151 Log: Add a TestFloat based test suite for floating-point implementations currently supporting sparc64. After a `make depend all` there are three programs; testsoftfloat for testing against the SoftFloat in src/lib/libc/softfloat for reference purposes, testemufloat for testing the emulator source in src/lib/libc/sparc64/fpu and testfloat for testing with the installed libc. Support for other architectures can be added as needed. PR: 144900 Submitted by: Peter Jeremy Added: head/tools/test/testfloat/ head/tools/test/testfloat/README.txt - copied unchanged from r207134, vendor/testfloat/dist/testfloat/README.txt head/tools/test/testfloat/fail.c - copied unchanged from r207134, vendor/testfloat/dist/testfloat/fail.c head/tools/test/testfloat/fail.h - copied unchanged from r207134, vendor/testfloat/dist/testfloat/fail.h head/tools/test/testfloat/random.c (contents, props changed) - copied, changed from r207134, vendor/testfloat/dist/testfloat/random.c head/tools/test/testfloat/random.h - copied unchanged from r207134, vendor/testfloat/dist/testfloat/random.h head/tools/test/testfloat/slowfloat-32.c - copied unchanged from r207134, vendor/testfloat/dist/testfloat/slowfloat-32.c head/tools/test/testfloat/slowfloat-64.c - copied unchanged from r207134, vendor/testfloat/dist/testfloat/slowfloat-64.c head/tools/test/testfloat/slowfloat.c - copied unchanged from r207134, vendor/testfloat/dist/testfloat/slowfloat.c head/tools/test/testfloat/slowfloat.h - copied unchanged from r207134, vendor/testfloat/dist/testfloat/slowfloat.h head/tools/test/testfloat/sparc64/ head/tools/test/testfloat/sparc64/Makefile (contents, props changed) head/tools/test/testfloat/sparc64/fpu_emul.S (contents, props changed) head/tools/test/testfloat/sparc64/fpu_reg.h (contents, props changed) head/tools/test/testfloat/sparc64/fpu_util.c (contents, props changed) head/tools/test/testfloat/sparc64/libc_private.h (contents, props changed) head/tools/test/testfloat/sparc64/milieu.h (contents, props changed) head/tools/test/testfloat/sparc64/namespace.h (contents, props changed) head/tools/test/testfloat/sparc64/softfloat.h (contents, props changed) head/tools/test/testfloat/sparc64/sparc64.h (contents, props changed) head/tools/test/testfloat/sparc64/systflags.c (contents, props changed) head/tools/test/testfloat/sparc64/systfloat.S (contents, props changed) head/tools/test/testfloat/sparc64/systfloat.h (contents, props changed) head/tools/test/testfloat/sparc64/systmodes.c (contents, props changed) head/tools/test/testfloat/sparc64/un-namespace.h (contents, props changed) head/tools/test/testfloat/systemBugs.txt - copied unchanged from r207134, vendor/testfloat/dist/testfloat/systemBugs.txt head/tools/test/testfloat/systflags.h - copied unchanged from r207134, vendor/testfloat/dist/testfloat/systflags.h head/tools/test/testfloat/systfloat.c - copied unchanged from r207134, vendor/testfloat/dist/testfloat/systfloat.c head/tools/test/testfloat/systmodes.h - copied unchanged from r207134, vendor/testfloat/dist/testfloat/systmodes.h head/tools/test/testfloat/testCases.c (contents, props changed) - copied, changed from r207134, vendor/testfloat/dist/testfloat/testCases.c head/tools/test/testfloat/testCases.h - copied unchanged from r207134, vendor/testfloat/dist/testfloat/testCases.h head/tools/test/testfloat/testFunction.c - copied unchanged from r207134, vendor/testfloat/dist/testfloat/testFunction.c head/tools/test/testfloat/testFunction.h - copied unchanged from r207134, vendor/testfloat/dist/testfloat/testFunction.h head/tools/test/testfloat/testLoops.c - copied unchanged from r207134, vendor/testfloat/dist/testfloat/testLoops.c head/tools/test/testfloat/testLoops.h - copied unchanged from r207134, vendor/testfloat/dist/testfloat/testLoops.h head/tools/test/testfloat/testfloat-history.txt - copied unchanged from r207134, vendor/testfloat/dist/testfloat/testfloat-history.txt head/tools/test/testfloat/testfloat-source.txt - copied unchanged from r207134, vendor/testfloat/dist/testfloat/testfloat-source.txt head/tools/test/testfloat/testfloat.c (contents, props changed) - copied, changed from r207134, vendor/testfloat/dist/testfloat/testfloat.c head/tools/test/testfloat/testfloat.txt - copied unchanged from r207134, vendor/testfloat/dist/testfloat/testfloat.txt head/tools/test/testfloat/testsoftfloat.c (contents, props changed) - copied, changed from r207134, vendor/testfloat/dist/testfloat/testsoftfloat.c head/tools/test/testfloat/writeHex.c - copied unchanged from r207134, vendor/testfloat/dist/testfloat/writeHex.c head/tools/test/testfloat/writeHex.h - copied unchanged from r207134, vendor/testfloat/dist/testfloat/writeHex.h Modified: head/tools/test/README Modified: head/tools/test/README ============================================================================== --- head/tools/test/README Sat Apr 24 10:22:08 2010 (r207150) +++ head/tools/test/README Sat Apr 24 12:11:41 2010 (r207151) @@ -11,3 +11,4 @@ devrandom Programs to test /dev/*random. dtrace DTrace test suite malloc A program to test and benchmark malloc(). posixshm A program to test POSIX shared memory. +testfloat Programs to test floating-point implementations Copied: head/tools/test/testfloat/README.txt (from r207134, vendor/testfloat/dist/testfloat/README.txt) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/tools/test/testfloat/README.txt Sat Apr 24 12:11:41 2010 (r207151, copy of r207134, vendor/testfloat/dist/testfloat/README.txt) @@ -0,0 +1,50 @@ + +Package Overview for TestFloat Release 2a + +John R. Hauser +1998 December 16 + + +TestFloat is a program for testing that a floating-point implementation +conforms to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. +TestFloat is distributed in the form of C source code. The TestFloat +package actually provides two related programs: + +-- The `testfloat' program tests a system's floating-point for conformance + to the IEC/IEEE Standard. This program uses the SoftFloat software + floating-point implementation as a basis for comparison. + +-- The `testsoftfloat' program tests SoftFloat itself for conformance to + the IEC/IEEE Standard. These tests are performed by comparing against a + separate, slower software floating-point that is included in the TestFloat + package. + +TestFloat depends on SoftFloat, but SoftFloat is not included in the +TestFloat package. SoftFloat can be obtained through the Web page `http:// +HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/SoftFloat.html'. + +TestFloat is documented in three text files: + + testfloat.txt Documentation for using the TestFloat programs + (both `testfloat' and `testsoftfloat'). + testfloat-source.txt Documentation for porting and compiling TestFloat. + testfloat-history.txt History of major changes to TestFloat. + +The following file is also provided: + + systemBugs.txt Information about processor bugs found using + TestFloat. + +Other files in the package comprise the source code for TestFloat. + +Please be aware that some work is involved in porting this software to other +targets. It is not just a matter of getting `make' to complete without +error messages. I would have written the code that way if I could, but +there are fundamental differences between systems that I can't make go away. +You should not attempt to compile the TestFloat sources without first +reading `testfloat-source.txt'. + +At the time of this writing, the most up-to-date information about +TestFloat and the latest release can be found at the Web page `http:// +HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/TestFloat.html'. + Copied: head/tools/test/testfloat/fail.c (from r207134, vendor/testfloat/dist/testfloat/fail.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/tools/test/testfloat/fail.c Sat Apr 24 12:11:41 2010 (r207151, copy of r207134, vendor/testfloat/dist/testfloat/fail.c) @@ -0,0 +1,46 @@ + +/* +=============================================================================== + +This C source file is part of TestFloat, Release 2a, a package of programs +for testing the correctness of floating-point arithmetic complying to the +IEC/IEEE Standard for Floating-Point. + +Written by John R. Hauser. More information is available through the Web +page `http://HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/TestFloat.html'. + +THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort +has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT +TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO +PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY +AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. + +Derivative works are acceptable, even for commercial purposes, so long as +(1) they include prominent notice that the work is derivative, and (2) they +include prominent notice akin to these four paragraphs for those parts of +this code that are retained. + +=============================================================================== +*/ + +#include <stdlib.h> +#include <stdarg.h> +#include <stdio.h> +#include "milieu.h" +#include "fail.h" + +char *fail_programName = ""; + +void fail( const char *message, ... ) +{ + va_list varArgs; + + fprintf( stderr, "%s: ", fail_programName ); + va_start( varArgs, message ); + vfprintf( stderr, message, varArgs ); + va_end( varArgs ); + fputs( ".\n", stderr ); + exit( EXIT_FAILURE ); + +} + Copied: head/tools/test/testfloat/fail.h (from r207134, vendor/testfloat/dist/testfloat/fail.h) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/tools/test/testfloat/fail.h Sat Apr 24 12:11:41 2010 (r207151, copy of r207134, vendor/testfloat/dist/testfloat/fail.h) @@ -0,0 +1,29 @@ + +/* +=============================================================================== + +This C header file is part of TestFloat, Release 2a, a package of programs +for testing the correctness of floating-point arithmetic complying to the +IEC/IEEE Standard for Floating-Point. + +Written by John R. Hauser. More information is available through the Web +page `http://HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/TestFloat.html'. + +THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort +has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT +TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO +PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY +AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. + +Derivative works are acceptable, even for commercial purposes, so long as +(1) they include prominent notice that the work is derivative, and (2) they +include prominent notice akin to these four paragraphs for those parts of +this code that are retained. + +=============================================================================== +*/ + +extern char *fail_programName; + +void fail( const char *, ... ); + Copied and modified: head/tools/test/testfloat/random.c (from r207134, vendor/testfloat/dist/testfloat/random.c) ============================================================================== --- vendor/testfloat/dist/testfloat/random.c Fri Apr 23 19:48:31 2010 (r207134, copy source) +++ head/tools/test/testfloat/random.c Sat Apr 24 12:11:41 2010 (r207151) @@ -23,6 +23,9 @@ this code that are retained. =============================================================================== */ +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + #include <stdlib.h> #include "milieu.h" #include "random.h" @@ -30,26 +33,21 @@ this code that are retained. uint8 randomUint8( void ) { - return (bits8) ( rand()>>4 ); + return (bits8) ( random()>>4 ); } uint16 randomUint16( void ) { - return ( ( rand() & 0x0FF0 )<<4 ) | ( ( rand()>>4 ) & 0xFF ); + return ( random() & 0x0000ffff ); } uint32 randomUint32( void ) { - return - ( ( (uint32) ( rand() & 0x0FF0 ) )<<20 ) - | ( ( (uint32) ( rand() & 0x0FF0 ) )<<12 ) - | ( ( rand() & 0x0FF0 )<<4 ) - | ( ( rand()>>4 ) & 0xFF ); - + return ( ( (uint32) random()<<16) | ( (uint32) random() & 0x0000ffff) ); } #ifdef BITS64 Copied: head/tools/test/testfloat/random.h (from r207134, vendor/testfloat/dist/testfloat/random.h) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/tools/test/testfloat/random.h Sat Apr 24 12:11:41 2010 (r207151, copy of r207134, vendor/testfloat/dist/testfloat/random.h) @@ -0,0 +1,32 @@ + +/* +=============================================================================== + +This C header file is part of TestFloat, Release 2a, a package of programs +for testing the correctness of floating-point arithmetic complying to the +IEC/IEEE Standard for Floating-Point. + +Written by John R. Hauser. More information is available through the Web +page `http://HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/TestFloat.html'. + +THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort +has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT +TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO +PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY +AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. + +Derivative works are acceptable, even for commercial purposes, so long as +(1) they include prominent notice that the work is derivative, and (2) they +include prominent notice akin to these four paragraphs for those parts of +this code that are retained. + +=============================================================================== +*/ + +uint8 randomUint8( void ); +uint16 randomUint16( void ); +uint32 randomUint32( void ); +#ifdef BITS64 +uint64 randomUint64( void ); +#endif + Copied: head/tools/test/testfloat/slowfloat-32.c (from r207134, vendor/testfloat/dist/testfloat/slowfloat-32.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/tools/test/testfloat/slowfloat-32.c Sat Apr 24 12:11:41 2010 (r207151, copy of r207134, vendor/testfloat/dist/testfloat/slowfloat-32.c) @@ -0,0 +1,1183 @@ + +/* +=============================================================================== + +This C source file is part of TestFloat, Release 2a, a package of programs +for testing the correctness of floating-point arithmetic complying to the +IEC/IEEE Standard for Floating-Point. + +Written by John R. Hauser. More information is available through the Web +page `http://HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/TestFloat.html'. + +THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort +has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT +TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO +PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY +AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. + +Derivative works are acceptable, even for commercial purposes, so long as +(1) they include prominent notice that the work is derivative, and (2) they +include prominent notice akin to these four paragraphs for those parts of +this code that are retained. + +=============================================================================== +*/ + +int8 slow_float_rounding_mode; +int8 slow_float_exception_flags; +int8 slow_float_detect_tininess; + +typedef struct { + bits32 a0, a1; +} bits64X; + +typedef struct { + flag isNaN; + flag isInf; + flag isZero; + flag sign; + int16 exp; + bits64X sig; +} floatX; + +static const floatX floatXNaN = { TRUE, FALSE, FALSE, FALSE, 0, { 0, 0 } }; +static const floatX floatXPositiveZero = + { FALSE, FALSE, TRUE, FALSE, 0, { 0, 0 } }; +static const floatX floatXNegativeZero = + { FALSE, FALSE, TRUE, TRUE, 0, { 0, 0 } }; + +static bits64X shortShift64Left( bits64X a, int8 shiftCount ) +{ + int8 negShiftCount; + + negShiftCount = ( - shiftCount & 31 ); + a.a0 = ( a.a0<<shiftCount ) | ( a.a1>>negShiftCount ); + a.a1 <<= shiftCount; + return a; + +} + +static bits64X shortShift64RightJamming( bits64X a, int8 shiftCount ) +{ + int8 negShiftCount; + bits32 extra; + + negShiftCount = ( - shiftCount & 31 ); + extra = a.a1<<negShiftCount; + a.a1 = ( a.a0<<negShiftCount ) | ( a.a1>>shiftCount ) | ( extra != 0 ); + a.a0 >>= shiftCount; + return a; + +} + +static bits64X neg64( bits64X a ) +{ + + if ( a.a1 == 0 ) { + a.a0 = - a.a0; + } + else { + a.a1 = - a.a1; + a.a0 = ~ a.a0; + } + return a; + +} + +static bits64X add64( bits64X a, bits64X b ) +{ + + a.a1 += b.a1; + a.a0 += b.a0 + ( a.a1 < b.a1 ); + return a; + +} + +static flag eq64( bits64X a, bits64X b ) +{ + + return ( a.a0 == b.a0 ) && ( a.a1 == b.a1 ); + +} + +static flag le64( bits64X a, bits64X b ) +{ + + return ( a.a0 < b.a0 ) || ( ( a.a0 == b.a0 ) && ( a.a1 <= b.a1 ) ); + +} + +static flag lt64( bits64X a, bits64X b ) +{ + + return ( a.a0 < b.a0 ) || ( ( a.a0 == b.a0 ) && ( a.a1 < b.a1 ) ); + +} + +static floatX roundFloatXTo24( flag isTiny, floatX zx ) +{ + + if ( zx.sig.a1 ) { + slow_float_exception_flags |= float_flag_inexact; + if ( isTiny ) slow_float_exception_flags |= float_flag_underflow; + switch ( slow_float_rounding_mode ) { + case float_round_nearest_even: + if ( zx.sig.a1 < 0x80000000 ) goto noIncrement; + if ( ( zx.sig.a1 == 0x80000000 ) && ! ( zx.sig.a0 & 1 ) ) { + goto noIncrement; + } + break; + case float_round_to_zero: + goto noIncrement; + case float_round_down: + if ( ! zx.sign ) goto noIncrement; + break; + case float_round_up: + if ( zx.sign ) goto noIncrement; + break; + } + ++zx.sig.a0; + if ( zx.sig.a0 == 0x01000000 ) { + zx.sig.a0 = 0x00800000; + ++zx.exp; + } + } + noIncrement: + zx.sig.a1 = 0; + return zx; + +} + +static floatX roundFloatXTo53( flag isTiny, floatX zx ) +{ + int8 roundBits; + + roundBits = zx.sig.a1 & 7; + zx.sig.a1 -= roundBits; + if ( roundBits ) { + slow_float_exception_flags |= float_flag_inexact; + if ( isTiny ) slow_float_exception_flags |= float_flag_underflow; + switch ( slow_float_rounding_mode ) { + case float_round_nearest_even: + if ( roundBits < 4 ) goto noIncrement; + if ( ( roundBits == 4 ) && ! ( zx.sig.a1 & 8 ) ) goto noIncrement; + break; + case float_round_to_zero: + goto noIncrement; + case float_round_down: + if ( ! zx.sign ) goto noIncrement; + break; + case float_round_up: + if ( zx.sign ) goto noIncrement; + break; + } + zx.sig.a1 += 8; + zx.sig.a0 += ( zx.sig.a1 == 0 ); + if ( zx.sig.a0 == 0x01000000 ) { + zx.sig.a0 = 0x00800000; + ++zx.exp; + } + } + noIncrement: + return zx; + +} + +static floatX int32ToFloatX( int32 a ) +{ + floatX ax; + + ax.isNaN = FALSE; + ax.isInf = FALSE; + ax.sign = ( a < 0 ); + ax.sig.a1 = ax.sign ? - a : a; + ax.sig.a0 = 0; + if ( a == 0 ) { + ax.isZero = TRUE; + return ax; + } + ax.isZero = FALSE; + ax.sig = shortShift64Left( ax.sig, 23 ); + ax.exp = 32; + while ( ax.sig.a0 < 0x00800000 ) { + ax.sig = shortShift64Left( ax.sig, 1 ); + --ax.exp; + } + return ax; + +} + +static int32 floatXToInt32( floatX ax ) +{ + int8 savedExceptionFlags; + int16 shiftCount; + int32 z; + + if ( ax.isInf || ax.isNaN ) { + slow_float_exception_flags |= float_flag_invalid; + return ( ax.isInf & ax.sign ) ? 0x80000000 : 0x7FFFFFFF; + } + if ( ax.isZero ) return 0; + savedExceptionFlags = slow_float_exception_flags; + shiftCount = 52 - ax.exp; + if ( 56 < shiftCount ) { + ax.sig.a1 = 1; + ax.sig.a0 = 0; + } + else { + while ( 0 < shiftCount ) { + ax.sig = shortShift64RightJamming( ax.sig, 1 ); + --shiftCount; + } + } + ax = roundFloatXTo53( FALSE, ax ); + ax.sig = shortShift64RightJamming( ax.sig, 3 ); + z = ax.sig.a1; + if ( ax.sign ) z = - z; + if ( ( shiftCount < 0 ) + || ax.sig.a0 + || ( ( z != 0 ) && ( ( ax.sign ^ ( z < 0 ) ) != 0 ) ) + ) { + slow_float_exception_flags = savedExceptionFlags | float_flag_invalid; + return ax.sign ? 0x80000000 : 0x7FFFFFFF; + } + return z; + +} + +static floatX float32ToFloatX( float32 a ) +{ + int16 expField; + floatX ax; + + ax.isNaN = FALSE; + ax.isInf = FALSE; + ax.isZero = FALSE; + ax.sign = ( ( a & 0x80000000 ) != 0 ); + expField = ( a>>23 ) & 0xFF; + ax.sig.a1 = 0; + ax.sig.a0 = a & 0x007FFFFF; + if ( expField == 0 ) { + if ( ax.sig.a0 == 0 ) { + ax.isZero = TRUE; + } + else { + expField = 1 - 0x7F; + do { + ax.sig.a0 <<= 1; + --expField; + } while ( ax.sig.a0 < 0x00800000 ); + ax.exp = expField; + } + } + else if ( expField == 0xFF ) { + if ( ax.sig.a0 == 0 ) { + ax.isInf = TRUE; + } + else { + ax.isNaN = TRUE; + } + } + else { + ax.sig.a0 |= 0x00800000; + ax.exp = expField - 0x7F; + } + return ax; + +} + +static float32 floatXToFloat32( floatX zx ) +{ + floatX savedZ; + flag isTiny; + int16 expField; + float32 z; + + if ( zx.isZero ) return zx.sign ? 0x80000000 : 0; + if ( zx.isInf ) return zx.sign ? 0xFF800000 : 0x7F800000; + if ( zx.isNaN ) return 0xFFFFFFFF; + while ( 0x01000000 <= zx.sig.a0 ) { + zx.sig = shortShift64RightJamming( zx.sig, 1 ); + ++zx.exp; + } + while ( zx.sig.a0 < 0x00800000 ) { + zx.sig = shortShift64Left( zx.sig, 1 ); + --zx.exp; + } + savedZ = zx; + isTiny = + ( slow_float_detect_tininess == float_tininess_before_rounding ) + && ( zx.exp + 0x7F <= 0 ); + zx = roundFloatXTo24( isTiny, zx ); + expField = zx.exp + 0x7F; + if ( 0xFF <= expField ) { + slow_float_exception_flags |= + float_flag_overflow | float_flag_inexact; + if ( zx.sign ) { + switch ( slow_float_rounding_mode ) { + case float_round_nearest_even: + case float_round_down: + z = 0xFF800000; + break; + case float_round_to_zero: + case float_round_up: + z = 0xFF7FFFFF; + break; + } + } + else { + switch ( slow_float_rounding_mode ) { + case float_round_nearest_even: + case float_round_up: + z = 0x7F800000; + break; + case float_round_to_zero: + case float_round_down: + z = 0x7F7FFFFF; + break; + } + } + return z; + } + if ( expField <= 0 ) { + isTiny = TRUE; + zx = savedZ; + expField = zx.exp + 0x7F; + if ( expField < -27 ) { + zx.sig.a1 = ( zx.sig.a0 != 0 ) || ( zx.sig.a1 != 0 ); + zx.sig.a0 = 0; + } + else { + while ( expField <= 0 ) { + zx.sig = shortShift64RightJamming( zx.sig, 1 ); + ++expField; + } + } + zx = roundFloatXTo24( isTiny, zx ); + expField = ( 0x00800000 <= zx.sig.a0 ) ? 1 : 0; + } + z = expField; + z <<= 23; + if ( zx.sign ) z |= 0x80000000; + z |= zx.sig.a0 & 0x007FFFFF; + return z; + +} + +static floatX float64ToFloatX( float64 a ) +{ + int16 expField; + floatX ax; + + ax.isNaN = FALSE; + ax.isInf = FALSE; + ax.isZero = FALSE; +#ifdef BITS64 + ax.sign = ( ( a & LIT64( 0x8000000000000000 ) ) != 0 ); + expField = ( a>>52 ) & 0x7FF; + ax.sig.a1 = a; + ax.sig.a0 = ( a>>32 ) & 0x000FFFFF; +#else + ax.sign = ( ( a.high & 0x80000000 ) != 0 ); + expField = ( a.high>>( 52 - 32 ) ) & 0x7FF; + ax.sig.a1 = a.low; + ax.sig.a0 = a.high & 0x000FFFFF; +#endif + if ( expField == 0 ) { + if ( ( ax.sig.a0 == 0 ) && ( ax.sig.a1 == 0 ) ) { + ax.isZero = TRUE; + } + else { + expField = 1 - 0x3FF; + do { + ax.sig = shortShift64Left( ax.sig, 1 ); + --expField; + } while ( ax.sig.a0 < 0x00100000 ); + ax.exp = expField; + } + } + else if ( expField == 0x7FF ) { + if ( ( ax.sig.a0 == 0 ) && ( ax.sig.a1 == 0 ) ) { + ax.isInf = TRUE; + } + else { + ax.isNaN = TRUE; + } + } + else { + ax.exp = expField - 0x3FF; + ax.sig.a0 |= 0x00100000; + } + ax.sig = shortShift64Left( ax.sig, 3 ); + return ax; + +} + +static float64 floatXToFloat64( floatX zx ) +{ + floatX savedZ; + flag isTiny; + int16 expField; + float64 z; + +#ifdef BITS64 + if ( zx.isZero ) return zx.sign ? LIT64( 0x8000000000000000 ) : 0; + if ( zx.isInf ) { + return + zx.sign ? LIT64( 0xFFF0000000000000 ) + : LIT64( 0x7FF0000000000000 ); + } + if ( zx.isNaN ) return LIT64( 0xFFFFFFFFFFFFFFFF ); +#else + if ( zx.isZero ) { + z.low = 0; + z.high = zx.sign ? 0x80000000 : 0; + return z; + } + if ( zx.isInf ) { + z.low = 0; + z.high = zx.sign ? 0xFFF00000 : 0x7FF00000; + return z; + } + if ( zx.isNaN ) { + z.high = z.low = 0xFFFFFFFF; + return z; + } +#endif + while ( 0x01000000 <= zx.sig.a0 ) { + zx.sig = shortShift64RightJamming( zx.sig, 1 ); + ++zx.exp; + } + while ( zx.sig.a0 < 0x00800000 ) { + zx.sig = shortShift64Left( zx.sig, 1 ); + --zx.exp; + } + savedZ = zx; + isTiny = + ( slow_float_detect_tininess == float_tininess_before_rounding ) + && ( zx.exp + 0x3FF <= 0 ); + zx = roundFloatXTo53( isTiny, zx ); + expField = zx.exp + 0x3FF; + if ( 0x7FF <= expField ) { + slow_float_exception_flags |= + float_flag_overflow | float_flag_inexact; +#ifdef BITS64 + if ( zx.sign ) { + switch ( slow_float_rounding_mode ) { + case float_round_nearest_even: + case float_round_down: + z = LIT64( 0xFFF0000000000000 ); + break; + case float_round_to_zero: + case float_round_up: + z = LIT64( 0xFFEFFFFFFFFFFFFF ); + break; + } + } + else { + switch ( slow_float_rounding_mode ) { + case float_round_nearest_even: + case float_round_up: + z = LIT64( 0x7FF0000000000000 ); + break; + case float_round_to_zero: + case float_round_down: + z = LIT64( 0x7FEFFFFFFFFFFFFF ); + break; + } + } +#else + if ( zx.sign ) { + switch ( slow_float_rounding_mode ) { + case float_round_nearest_even: + case float_round_down: + z.low = 0; + z.high = 0xFFF00000; + break; + case float_round_to_zero: + case float_round_up: + z.low = 0xFFFFFFFF; + z.high = 0xFFEFFFFF; + break; + } + } + else { + switch ( slow_float_rounding_mode ) { + case float_round_nearest_even: + case float_round_up: + z.low = 0; + z.high = 0x7FF00000; + break; + case float_round_to_zero: + case float_round_down: + z.low = 0xFFFFFFFF; + z.high = 0x7FEFFFFF; + break; + } + } +#endif + return z; + } + if ( expField <= 0 ) { + isTiny = TRUE; + zx = savedZ; + expField = zx.exp + 0x3FF; + if ( expField < -56 ) { + zx.sig.a1 = ( zx.sig.a0 != 0 ) || ( zx.sig.a1 != 0 ); + zx.sig.a0 = 0; + } + else { + while ( expField <= 0 ) { + zx.sig = shortShift64RightJamming( zx.sig, 1 ); + ++expField; + } + } + zx = roundFloatXTo53( isTiny, zx ); + expField = ( 0x00800000 <= zx.sig.a0 ) ? 1 : 0; + } + zx.sig = shortShift64RightJamming( zx.sig, 3 ); +#ifdef BITS64 + z = expField; + z <<= 52; + if ( zx.sign ) z |= LIT64( 0x8000000000000000 ); + z |= ( ( (bits64) ( zx.sig.a0 & 0x000FFFFF ) )<<32 ) | zx.sig.a1; +#else + z.low = zx.sig.a1; + z.high = expField; + z.high <<= 52 - 32; + if ( zx.sign ) z.high |= 0x80000000; + z.high |= zx.sig.a0 & 0x000FFFFF; +#endif + return z; + +} + +static floatX floatXInvalid( void ) +{ + + slow_float_exception_flags |= float_flag_invalid; + return floatXNaN; + +} + +static floatX floatXRoundToInt( floatX ax ) +{ + int16 shiftCount, i; + + if ( ax.isNaN || ax.isInf ) return ax; + shiftCount = 52 - ax.exp; + if ( shiftCount <= 0 ) return ax; + if ( 55 < shiftCount ) { + ax.exp = 52; + ax.sig.a1 = ! ax.isZero; + ax.sig.a0 = 0; + } + else { + while ( 0 < shiftCount ) { + ax.sig = shortShift64RightJamming( ax.sig, 1 ); + ++ax.exp; + --shiftCount; + } + } + ax = roundFloatXTo53( FALSE, ax ); + if ( ( ax.sig.a0 == 0 ) && ( ax.sig.a1 == 0 ) ) ax.isZero = TRUE; + return ax; + +} + +static floatX floatXAdd( floatX ax, floatX bx ) +{ + int16 expDiff; + floatX zx; + + if ( ax.isNaN ) return ax; + if ( bx.isNaN ) return bx; + if ( ax.isInf && bx.isInf ) { + if ( ax.sign == bx.sign ) return ax; + return floatXInvalid(); + } + if ( ax.isInf ) return ax; + if ( bx.isInf ) return bx; + if ( ax.isZero && bx.isZero ) { + if ( ax.sign == bx.sign ) return ax; + goto completeCancellation; + } + if ( ( ax.sign != bx.sign ) + && ( ax.exp == bx.exp ) + && eq64( ax.sig, bx.sig ) + ) { + completeCancellation: + return + ( slow_float_rounding_mode == float_round_down ) ? + floatXNegativeZero + : floatXPositiveZero; + } + if ( ax.isZero ) return bx; + if ( bx.isZero ) return ax; + expDiff = ax.exp - bx.exp; + if ( expDiff < 0 ) { + zx = ax; + zx.exp = bx.exp; + if ( expDiff < -56 ) { + zx.sig.a1 = 1; + zx.sig.a0 = 0; + } + else { + while ( expDiff < 0 ) { + zx.sig = shortShift64RightJamming( zx.sig, 1 ); + ++expDiff; + } + } + if ( ax.sign != bx.sign ) zx.sig = neg64( zx.sig ); + zx.sign = bx.sign; + zx.sig = add64( zx.sig, bx.sig ); + } + else { + zx = bx; + zx.exp = ax.exp; + if ( 56 < expDiff ) { + zx.sig.a1 = 1; + zx.sig.a0 = 0; + } + else { + while ( 0 < expDiff ) { + zx.sig = shortShift64RightJamming( zx.sig, 1 ); + --expDiff; + } + } + if ( ax.sign != bx.sign ) zx.sig = neg64( zx.sig ); + zx.sign = ax.sign; + zx.sig = add64( zx.sig, ax.sig ); + } + if ( zx.sig.a0 & 0x80000000 ) { + zx.sig = neg64( zx.sig ); + zx.sign = ! zx.sign; + } + return zx; + +} + +static floatX floatXMul( floatX ax, floatX bx ) +{ + int8 bitNum; + floatX zx; + + if ( ax.isNaN ) return ax; + if ( bx.isNaN ) return bx; + if ( ax.isInf ) { + if ( bx.isZero ) return floatXInvalid(); + if ( bx.sign ) ax.sign = ! ax.sign; + return ax; + } + if ( bx.isInf ) { + if ( ax.isZero ) return floatXInvalid(); + if ( ax.sign ) bx.sign = ! bx.sign; + return bx; + } + zx = ax; + zx.sign ^= bx.sign; + if ( ax.isZero || bx.isZero ) { + return zx.sign ? floatXNegativeZero : floatXPositiveZero; + } + zx.exp += bx.exp + 1; + zx.sig.a1 = 0; + zx.sig.a0 = 0; + for ( bitNum = 0; bitNum < 55; ++bitNum ) { + if ( bx.sig.a1 & 2 ) zx.sig = add64( zx.sig, ax.sig ); + bx.sig = shortShift64RightJamming( bx.sig, 1 ); + zx.sig = shortShift64RightJamming( zx.sig, 1 ); + } + return zx; + +} + +static floatX floatXDiv( floatX ax, floatX bx ) +{ + bits64X negBSig; + int8 bitNum; + floatX zx; + + if ( ax.isNaN ) return ax; + if ( bx.isNaN ) return bx; + if ( ax.isInf ) { + if ( bx.isInf ) return floatXInvalid(); + if ( bx.sign ) ax.sign = ! ax.sign; + return ax; + } + if ( bx.isZero ) { + if ( ax.isZero ) return floatXInvalid(); + slow_float_exception_flags |= float_flag_divbyzero; + if ( ax.sign ) bx.sign = ! bx.sign; + bx.isZero = FALSE; + bx.isInf = TRUE; + return bx; + } + zx = ax; + zx.sign ^= bx.sign; + if ( ax.isZero || bx.isInf ) { + return zx.sign ? floatXNegativeZero : floatXPositiveZero; + } + zx.exp -= bx.exp + 1; + zx.sig.a1 = 0; + zx.sig.a0 = 0; + negBSig = neg64( bx.sig ); + for ( bitNum = 0; bitNum < 56; ++bitNum ) { + if ( le64( bx.sig, ax.sig ) ) { + zx.sig.a1 |= 1; + ax.sig = add64( ax.sig, negBSig ); + } + ax.sig = shortShift64Left( ax.sig, 1 ); + zx.sig = shortShift64Left( zx.sig, 1 ); + } + if ( ax.sig.a0 || ax.sig.a1 ) zx.sig.a1 |= 1; + return zx; + +} + +static floatX floatXRem( floatX ax, floatX bx ) +{ + bits64X negBSig; + flag lastQuotientBit; + bits64X savedASig; + + if ( ax.isNaN ) return ax; + if ( bx.isNaN ) return bx; + if ( ax.isInf || bx.isZero ) return floatXInvalid(); + if ( ax.isZero || bx.isInf ) return ax; + --bx.exp; + if ( ax.exp < bx.exp ) return ax; + bx.sig = shortShift64Left( bx.sig, 1 ); + negBSig = neg64( bx.sig ); + while ( bx.exp < ax.exp ) { + if ( le64( bx.sig, ax.sig ) ) ax.sig = add64( ax.sig, negBSig ); + ax.sig = shortShift64Left( ax.sig, 1 ); + --ax.exp; + } + lastQuotientBit = le64( bx.sig, ax.sig ); + if ( lastQuotientBit ) ax.sig = add64( ax.sig, negBSig ); + savedASig = ax.sig; + ax.sig = neg64( add64( ax.sig, negBSig ) ); + if ( lt64( ax.sig, savedASig ) ) { + ax.sign = ! ax.sign; + } + else if ( lt64( savedASig, ax.sig ) ) { + ax.sig = savedASig; + } + else { + if ( lastQuotientBit ) { + ax.sign = ! ax.sign; + } + else { + ax.sig = savedASig; + } + } + if ( ( ax.sig.a0 == 0 ) && ( ax.sig.a1 == 0 ) ) ax.isZero = TRUE; + return ax; + +} + +static floatX floatXSqrt( floatX ax ) *** DIFF OUTPUT TRUNCATED AT 1000 LINES *** _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Sun May 2 16:52:24 2010 New Revision: 207527 URL: http://svn.freebsd.org/changeset/base/207527 Log: MFC: r206490, r206492 While SPARC V9 allows tininess to be detected either before or after rounding (impl. dep. #55), the SPARC JPS1 responsible for SPARC64 and UltraSPARC processors defines that in all cases tininess is detected before rounding therefore rounding up to the smallest normalized number should set the underflow flag. This change is needed for using SoftFloat on sparc64 for reference purposes. PR: 144900 Submitted by: Peter Jeremy Modified: stable/7/lib/libc/softfloat/softfloat-specialize Directory Properties: stable/7/lib/libc/ (props changed) stable/7/lib/libc/stdtime/ (props changed) Modified: stable/7/lib/libc/softfloat/softfloat-specialize ============================================================================== --- stable/7/lib/libc/softfloat/softfloat-specialize Sun May 2 16:52:23 2010 (r207526) +++ stable/7/lib/libc/softfloat/softfloat-specialize Sun May 2 16:52:24 2010 (r207527) @@ -44,7 +44,11 @@ Underflow tininess-detection mode, stati #ifdef SOFTFLOAT_FOR_GCC static #endif +#ifdef __sparc64__ +int8 float_detect_tininess = float_tininess_before_rounding; +#else int8 float_detect_tininess = float_tininess_after_rounding; +#endif /* ------------------------------------------------------------------------------- _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Sun May 2 16:55:10 2010 New Revision: 207528 URL: http://svn.freebsd.org/changeset/base/207528 Log: MFC: r207151 Add a TestFloat based test suite for floating-point implementations currently supporting sparc64. After a `make depend all` there are three programs; testsoftfloat for testing against the SoftFloat in src/lib/libc/softfloat for reference purposes, testemufloat for testing the emulator source in src/lib/libc/sparc64/fpu and testfloat for testing with the installed libc. Support for other architectures can be added as needed. PR: 144900 Submitted by: Peter Jeremy Added: stable/8/tools/test/testfloat/ - copied from r207151, head/tools/test/testfloat/ Modified: stable/8/tools/test/README Directory Properties: stable/8/tools/test/ (props changed) Modified: stable/8/tools/test/README ============================================================================== --- stable/8/tools/test/README Sun May 2 16:52:24 2010 (r207527) +++ stable/8/tools/test/README Sun May 2 16:55:10 2010 (r207528) @@ -11,3 +11,4 @@ devrandom Programs to test /dev/*random. dtrace DTrace test suite malloc A program to test and benchmark malloc(). posixshm A program to test POSIX shared memory. +testfloat Programs to test floating-point implementations _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
Author: marius Date: Sun May 2 16:55:13 2010 New Revision: 207529 URL: http://svn.freebsd.org/changeset/base/207529 Log: MFC: r207151 Add a TestFloat based test suite for floating-point implementations currently supporting sparc64. After a `make depend all` there are three programs; testsoftfloat for testing against the SoftFloat in src/lib/libc/softfloat for reference purposes, testemufloat for testing the emulator source in src/lib/libc/sparc64/fpu and testfloat for testing with the installed libc. Support for other architectures can be added as needed. PR: 144900 Submitted by: Peter Jeremy Added: stable/7/tools/test/testfloat/ - copied from r207151, head/tools/test/testfloat/ Modified: stable/7/tools/test/README Directory Properties: stable/7/tools/test/ (props changed) Modified: stable/7/tools/test/README ============================================================================== --- stable/7/tools/test/README Sun May 2 16:55:10 2010 (r207528) +++ stable/7/tools/test/README Sun May 2 16:55:13 2010 (r207529) @@ -10,3 +10,4 @@ Please make a subdir per program, and ad devrandom Programs to test /dev/*random. malloc A program to test and benchmark malloc(). posixshm A program to test POSIX shared memory. +testfloat Programs to test floating-point implementations _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
State Changed From-To: open->closed close