When TPC is enabled, the PHY doesn't necessarily clamp the TX power limit at the value programmed into the per-rate TX power registers.
For 11n chips, the HT20 and HT40 rates have a different adjustment to the programmed TX power values. Thus when doing TPC, the TX descriptor TX power register needs to be adjusted by that factor.
For later series chips (AR9280 and later), the TX descriptor TX power values need to be adjusted to account for the PHY minimum TX power being -2.5dBm, rather than 0 dBm (ie, instead of 0 == 0 dBm, 0 == -2.5dBm.)
For later later chips (AR9285), there are some differences between TX power levels for CCK, OFDM and HT rates.
How-To-Repeat: Enable TPC, see things go haywire.
Over to maintainer(s).
For bugs that match the following
- Status Is In progress
- Untouched since 2018-01-01.
- Affects Base System OR Documentation
Reset to open status.
I did a quick pass but if you are getting this email it might be worthwhile to double check to see if this bug ought to be closed.