Created attachment 153812 [details]
Do not assume, that SSE means SSE2 -- only enable SSE2 if explicitly requested
The existing port builds version 3.3.3, while the newer release -- 3.3.4 -- is available.
Both 3.3.3 and 3.3.4 have a problem with systems, where SSE is among processor-features, but SSE2 is not. For some reason, upstream code interprets "--enable-sse" to ALSO mean "--enable-sse2":
The attached patches attempts to both update our port to 3.3.4 and fix the SSE2-presumption.
It seems to build fine here (used for fftw3-float) and pass the "check" as well ("bigcheck" is just too long for this little Athlon).
Created attachment 153813 [details]
Update to 3.3.4
The upstream maintainer convinced me, my patch is not particularly helpful -- for it disables SSE altogether:
That -- disabling of SSE -- may be the only work-around for when clang is used on a CPU with SSE, but without SSE2. I can confirm, that gcc (4.2.2) has no problem compiling single-precision SSE for athlon-xp -- which is where clang (3.4.1) dies.
I'm building clang-3.6.0 now to investigate further.
(In reply to Mikhail Teterin from comment #2)
It's global issue isn't fftw3 only affected:
*** Bug 201265 has been marked as a duplicate of this bug. ***
I've updated fftw3 to 3.3.5. Upstream seems to have fixed the issue, but I've included a SIMD option to toggle the optimizations if all else fails. Flags weren't being set for clang either, but I've patched the port to set them.
Closing this. The upgrade part is done and I believe the SSE issue is resolved and I haven't heard any more feedback about it since I made the changes in October.