Bug 230761 - New port: cad/verilator: fastest free Verilog HDL simulator
Summary: New port: cad/verilator: fastest free Verilog HDL simulator
Status: Closed FIXED
Alias: None
Product: Ports & Packages
Classification: Unclassified
Component: Individual Port(s) (show other bugs)
Version: Latest
Hardware: Any Any
: --- Affects Only Me
Assignee: freebsd-ports-bugs (Nobody)
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2018-08-19 22:40 UTC by Kevin Zheng
Modified: 2019-01-17 23:28 UTC (History)
1 user (show)

See Also:


Attachments
Git style diff (4.31 KB, patch)
2018-08-19 22:40 UTC, Kevin Zheng
no flags Details | Diff
Old-style shar (4.10 KB, text/plain)
2018-08-19 22:41 UTC, Kevin Zheng
no flags Details

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Description Kevin Zheng 2018-08-19 22:40:17 UTC
Created attachment 196366 [details]
Git style diff

Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.

WWW: https://www.veripool.org/projects/verilator/wiki/Intro
Comment 1 Kevin Zheng 2018-08-19 22:41:15 UTC
Created attachment 196367 [details]
Old-style shar
Comment 2 Kevin Zheng 2018-09-26 22:54:41 UTC
Anyone able to take a look? It's been over a month.
Comment 3 commit-hook freebsd_committer 2019-01-17 23:27:38 UTC
A commit references this bug:

Author: swills
Date: Thu Jan 17 23:27:12 UTC 2019
New revision: 490609
URL: https://svnweb.freebsd.org/changeset/ports/490609

Log:
  cad/verilator: create port

  Verilator is the fastest free Verilog HDL simulator, and beats most commercial
  simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
  PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
  designed for large projects where fast simulation performance is of primary
  concern, and is especially well suited to generate executable models of CPUs
  for embedded software design teams.

  WWW: https://www.veripool.org/projects/verilator/wiki/Intro

  PR:		230761
  Submitted by:	Kevin Zheng <kevinz5000@gmail.com>

Changes:
  head/cad/Makefile
  head/cad/verilator/
  head/cad/verilator/Makefile
  head/cad/verilator/distinfo
  head/cad/verilator/pkg-descr
  head/cad/verilator/pkg-plist
Comment 4 Steve Wills freebsd_committer 2019-01-17 23:28:28 UTC
Committed, thanks for the work, sorry it took so long to get it committed.