Bug 237783 - audio/alsa-lib: clang crashes during build on armv6 with -fstack-protector-strong
Summary: audio/alsa-lib: clang crashes during build on armv6 with -fstack-protector-st...
Status: Closed DUPLICATE of bug 237074
Alias: None
Product: Ports & Packages
Classification: Unclassified
Component: Individual Port(s) (show other bugs)
Version: Latest
Hardware: arm Any
: --- Affects Only Me
Assignee: freebsd-toolchain (Nobody)
URL: http://beefy8.nyi.freebsd.org/data/he...
Keywords: needs-qa
: 237784 (view as bug list)
Depends on:
Blocks: 237273
  Show dependency treegraph
 
Reported: 2019-05-08 03:17 UTC by Jan Beich
Modified: 2019-05-11 09:57 UTC (History)
1 user (show)

See Also:


Attachments
src/seq/seq_midi_event.c (compressed, preprocessed) (92.24 KB, application/x-xz)
2019-05-08 03:17 UTC, Jan Beich
no flags Details
command line args (for clang 8) (2.56 KB, text/plain)
2019-05-08 03:18 UTC, Jan Beich
no flags Details

Note You need to log in before you can comment on or make changes to this bug.
Description Jan Beich freebsd_committer 2019-05-08 03:17:19 UTC
Created attachment 204253 [details]
src/seq/seq_midi_event.c (compressed, preprocessed)

/bin/sh ../../libtool  --tag=CC    --mode=compile /usr/bin/cc -DHAVE_CONFIG_H  -I. -I../../include  -I../../include -I/usr/ports/audio/alsa-lib/files   -O2 -pipe  -fstack-protector-strong -fno-strict-aliasing -MT seq_midi_event.lo -MD -MP -MF .deps/seq_midi_event.Tpo -c -o seq_midi_event.lo seq_midi_event.c
libtool: compile:  /usr/bin/cc -DHAVE_CONFIG_H -I. -I../../include -I../../include -I/usr/ports/audio/alsa-lib/files -O2 -pipe -fstack-protector-strong -fno-strict-aliasing -MT seq_midi_event.lo -MD -MP -MF .deps/seq_midi_event.Tpo -c seq_midi_event.c  -fPIC -DPIC -o .libs/seq_midi_event.o

# Machine code for function snd_midi_event_decode: NoPHIs, TracksLiveness
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=4, align=1, at location [SP]
Jump Tables:
%jump-table.0:  %bb.18 %bb.24 %bb.19 %bb.42 %bb.20 %bb.21 %bb.22 %bb.23 %bb.4 %bb.2 %bb.3 %bb.42 %bb.42 %bb.42 %bb.8 %bb.9 %bb.7 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.12 %bb.13 %bb.14 %bb.42 %bb.42 %bb.42 %bb.11 %bb.42 %bb.42 %bb.42 %bb.10 %bb.16 %bb.15 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.42 %bb.17
Function Live Ins: $r0 in %13, $r1 in %14, $r2 in %15, $r3 in %16

bb.0.entry:
  successors: %bb.44(0x02e8ba2f), %bb.1(0x7d1745d1); %bb.44(2.27%), %bb.1(97.73%)
  liveins: $r0, $r1, $r2, $r3
  %16:gpr = COPY killed $r3
  %15:gpr = COPY killed $r2
  %14:gpr = COPY killed $r1
  %13:gpr = COPY killed $r0
  %21:gpr = LDRLIT_ga_pcrel_ldr target-flags(arm-got) @__stack_chk_guard :: (load 4 from got)
  %22:gpr = LDRi12 %21:gpr, 0, 14, $noreg :: (volatile load 4 from @__stack_chk_guard)
  STRi12 %22:gpr, %stack.0.StackGuardSlot, 0, 14, $noreg :: (volatile store 4 into %stack.0.StackGuardSlot)
  %23:gprnopc = LDRBi12 %16:gpr, 0, 14, $noreg :: (load 1 from %ir.type1164, align 4)
  %20:gprnopc = SUBri %23:gprnopc, 6, 14, $noreg, $noreg
  %17:gpr = MVNi 1, 14, $noreg, $noreg
  CMPri %20:gprnopc, 124, 14, $noreg, implicit-def $cpsr
  Bcc %bb.1, 9, killed $cpsr

bb.44:
; predecessors: %bb.0
  successors: %bb.42(0x80000000); %bb.42(100.00%)

  %95:gpr = COPY %17:gpr
  B %bb.42

bb.1.entry:
; predecessors: %bb.0
  successors: %bb.18(0x05f417d0), %bb.24(0x05f417d0), %bb.19(0x05f417d0), %bb.42(0x02fa0be8), %bb.20(0x05f417d0), %bb.21(0x05f417d0), %bb.22(0x05f417d0), %bb.23(0x05f417d0), %bb.4(0x05f417d0), %bb.2(0x05f417d0), %bb.3(0x05f417d0), %bb.8(0x05f417d0), %bb.9(0x05f417d0), %bb.7(0x05f417d0), %bb.12(0x05f417d0), %bb.13(0x05f417d0), %bb.14(0x05f417d0), %bb.11(0x05f417d0), %bb.10(0x05f417d0), %bb.16(0x05f417d0), %bb.15(0x05f417d0), %bb.17(0x05f417d0); %bb.18(4.65%), %bb.24(4.65%), %bb.19(4.65%), %bb.42(2.33%), %bb.20(4.65%), %bb.21(4.65%), %bb.22(4.65%), %bb.23(4.65%), %bb.4(4.65%), %bb.2(4.65%), %bb.3(4.65%), %bb.8(4.65%), %bb.9(4.65%), %bb.7(4.65%), %bb.12(4.65%), %bb.13(4.65%), %bb.14(4.65%), %bb.11(4.65%), %bb.10(4.65%), %bb.16(4.65%), %bb.15(4.65%), %bb.17(4.65%)

  %19:gpr = MOVi 8, 14, $noreg, $noreg
  %18:gpr = MOVi 0, 14, $noreg, $noreg
  %24:gpr = LEApcrelJT %jump-table.0, 14, $noreg
  %25:gpr = LDRrs %24:gpr, %20:gprnopc, 16386, 14, $noreg :: (load 4 from jump-table)
  %88:gpr = COPY %18:gpr
  %89:gpr = COPY %19:gpr
  %90:gpr = COPY %18:gpr
  %95:gpr = COPY %17:gpr
  BR_JTadd %24:gpr, %25:gpr, %jump-table.0

bb.2.if.then21.fold.split:
; predecessors: %bb.1
  successors: %bb.4(0x80000000); %bb.4(100.00%)

  %26:gpr = MOVi 1, 14, $noreg, $noreg
  %88:gpr = COPY %26:gpr
  B %bb.4

bb.3.if.then21.fold.split149:
; predecessors: %bb.1
  successors: %bb.4(0x80000000); %bb.4(100.00%)

  %76:gpr = MOVi 2, 14, $noreg, $noreg
  %88:gpr = COPY %76:gpr

bb.4.if.then21:
; predecessors: %bb.1, %bb.2, %bb.3
  successors: %bb.6(0x7ffff800), %bb.5(0x00000800); %bb.6(100.00%), %bb.5(0.00%)

  %0:gpr = COPY %88:gpr
  %81:gpr = LDRi12 %21:gpr, 0, 14, $noreg :: (volatile load 4 from @__stack_chk_guard)
  %82:gpr = LDRi12 %stack.0.StackGuardSlot, 0, 14, $noreg :: (volatile load 4 from %stack.0.StackGuardSlot)
  dead %83:gpr = SUBrr %81:gpr, %82:gpr, 14, $noreg, def $cpsr
  Bcc %bb.5, 1, killed $cpsr
  B %bb.6

bb.5.if.then21:
; predecessors: %bb.4, %bb.42

  ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
  BL &__stack_chk_fail, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit-def $sp
  ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp

bb.6.if.then21:
; predecessors: %bb.4

  %77:gpr = LDRLIT_ga_pcrel @extra_event
  %78:gpr = ADDrsi %77:gpr, %0:gpr, 26, 14, $noreg, $noreg
  %79:tcgpr = LDRi12 %78:gpr, 4, 14, $noreg :: (load 4 from %ir.decode)
  TCRETURNri %79:tcgpr, implicit $sp, implicit $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3

bb.7.if.then29.fold.split:
; predecessors: %bb.1
  successors: %bb.17(0x80000000); %bb.17(100.00%)

  %36:gpr = MOVi 9, 14, $noreg, $noreg
  %89:gpr = COPY %36:gpr
  B %bb.17

bb.8.if.then29.fold.split155:
; predecessors: %bb.1
  successors: %bb.17(0x80000000); %bb.17(100.00%)

  %35:gpr = MOVi 10, 14, $noreg, $noreg
  %89:gpr = COPY %35:gpr
  B %bb.17

bb.9.if.then29.fold.split156:
; predecessors: %bb.1
  successors: %bb.17(0x80000000); %bb.17(100.00%)

  %34:gpr = MOVi 11, 14, $noreg, $noreg
  %89:gpr = COPY %34:gpr
  B %bb.17

bb.10.if.then29.fold.split157:
; predecessors: %bb.1
  successors: %bb.17(0x80000000); %bb.17(100.00%)

  %33:gpr = MOVi 14, 14, $noreg, $noreg
  %89:gpr = COPY %33:gpr
  B %bb.17

bb.11.if.then29.fold.split158:
; predecessors: %bb.1
  successors: %bb.17(0x80000000); %bb.17(100.00%)

  %32:gpr = MOVi 16, 14, $noreg, $noreg
  %89:gpr = COPY %32:gpr
  B %bb.17

bb.12.if.then29.fold.split159:
; predecessors: %bb.1
  successors: %bb.17(0x80000000); %bb.17(100.00%)

  %31:gpr = MOVi 18, 14, $noreg, $noreg
  %89:gpr = COPY %31:gpr
  B %bb.17

bb.13.if.then29.fold.split160:
; predecessors: %bb.1
  successors: %bb.17(0x80000000); %bb.17(100.00%)

  %30:gpr = MOVi 19, 14, $noreg, $noreg
  %89:gpr = COPY %30:gpr
  B %bb.17

bb.14.if.then29.fold.split161:
; predecessors: %bb.1
  successors: %bb.17(0x80000000); %bb.17(100.00%)

  %29:gpr = MOVi 20, 14, $noreg, $noreg
  %89:gpr = COPY %29:gpr
  B %bb.17

bb.15.if.then29.fold.split162:
; predecessors: %bb.1
  successors: %bb.17(0x80000000); %bb.17(100.00%)

  %28:gpr = MOVi 22, 14, $noreg, $noreg
  %89:gpr = COPY %28:gpr
  B %bb.17

bb.16.if.then29.fold.split163:
; predecessors: %bb.1
  successors: %bb.17(0x80000000); %bb.17(100.00%)

  %27:gpr = MOVi 23, 14, $noreg, $noreg
  %89:gpr = COPY %27:gpr

bb.17.if.then29:
; predecessors: %bb.1, %bb.16, %bb.15, %bb.14, %bb.13, %bb.12, %bb.11, %bb.10, %bb.9, %bb.8, %bb.7
  successors: %bb.25(0x80000000); %bb.25(100.00%)

  %1:gpr = COPY %89:gpr
  %2:gpr = nuw nsw ADDri %1:gpr, 232, 14, $noreg, $noreg
  %91:gprnopc = COPY %1:gpr
  %92:gprnopc = COPY %2:gpr
  B %bb.25

bb.18.if.else.fold.split:
; predecessors: %bb.1
  successors: %bb.24(0x80000000); %bb.24(100.00%)

  %42:gpr = MOVi 1, 14, $noreg, $noreg
  %90:gpr = COPY %42:gpr
  B %bb.24

bb.19.if.else.fold.split150:
; predecessors: %bb.1
  successors: %bb.24(0x80000000); %bb.24(100.00%)

  %41:gpr = MOVi 2, 14, $noreg, $noreg
  %90:gpr = COPY %41:gpr
  B %bb.24

bb.20.if.else.fold.split151:
; predecessors: %bb.1
  successors: %bb.24(0x80000000); %bb.24(100.00%)

  %40:gpr = MOVi 3, 14, $noreg, $noreg
  %90:gpr = COPY %40:gpr
  B %bb.24

bb.21.if.else.fold.split152:
; predecessors: %bb.1
  successors: %bb.24(0x80000000); %bb.24(100.00%)

  %39:gpr = MOVi 4, 14, $noreg, $noreg
  %90:gpr = COPY %39:gpr
  B %bb.24

bb.22.if.else.fold.split153:
; predecessors: %bb.1
  successors: %bb.24(0x80000000); %bb.24(100.00%)

  %38:gpr = MOVi 5, 14, $noreg, $noreg
  %90:gpr = COPY %38:gpr
  B %bb.24

bb.23.if.else.fold.split154:
; predecessors: %bb.1
  successors: %bb.24(0x80000000); %bb.24(100.00%)

  %37:gpr = MOVi 6, 14, $noreg, $noreg
  %90:gpr = COPY %37:gpr

bb.24.if.else:
; predecessors: %bb.1, %bb.23, %bb.22, %bb.21, %bb.20, %bb.19, %bb.18
  successors: %bb.25(0x80000000); %bb.25(100.00%)

  %3:gpr = COPY %90:gpr
  %43:gprnopc = LDRBi12 %16:gpr, 16, 14, $noreg :: (load 1 from %ir.channel, align 4)
  %44:gpr = ANDri %43:gprnopc, 15, 14, $noreg, $noreg
  %45:gpr = ORRrsi %44:gpr, %3:gpr, 34, 14, $noreg, $noreg
  %4:gpr = ORRri %45:gpr, 128, 14, $noreg, $noreg
  %91:gprnopc = COPY %3:gpr
  %92:gprnopc = COPY %4:gpr

bb.25.if.end32:
; predecessors: %bb.17, %bb.24
  successors: %bb.26(0x40000000), %bb.30(0x40000000); %bb.26(50.00%), %bb.30(50.00%)

  %6:gprnopc = COPY %92:gprnopc
  %5:gprnopc = COPY %91:gprnopc
  CMPri %6:gprnopc, 240, 14, $noreg, implicit-def $cpsr
  Bcc %bb.30, 1, killed $cpsr
  B %bb.26

bb.26.if.then35:
; predecessors: %bb.25
  successors: %bb.42(0x40000000), %bb.27(0x40000000); %bb.42(50.00%), %bb.27(50.00%)

  %71:gprnopc = MOVi 255, 14, $noreg, $noreg
  STRBi12 %71:gprnopc, %13:gpr, 12, 14, $noreg :: (store 1 into %ir.lastcmd.i, align 4)
  %7:gpr = LDRi12 %16:gpr, 16, 14, $noreg :: (load 4 from %ir.len)
  %70:gpr = MVNi 11, 14, $noreg, $noreg
  CMPrr %7:gpr, %15:gpr, 14, $noreg, implicit-def $cpsr
  %95:gpr = COPY %70:gpr
  Bcc %bb.42, 12, killed $cpsr
  B %bb.27

bb.27.if.end40:
; predecessors: %bb.26
  successors: %bb.28(0x30000000), %bb.29(0x50000000); %bb.28(37.50%), %bb.29(62.50%)

  %73:gprnopc = LDRBi12 %16:gpr, 1, 14, $noreg :: (load 1 from %ir.flags)
  TSTri %73:gprnopc, 12, 14, $noreg, implicit-def $cpsr
  Bcc %bb.29, 1, killed $cpsr

bb.28:
; predecessors: %bb.27
  successors: %bb.42(0x80000000); %bb.42(100.00%)

  %72:gpr = MVNi 21, 14, $noreg, $noreg
  %95:gpr = COPY %72:gpr
  B %bb.42

bb.29.sw.epilog:
; predecessors: %bb.27
  successors: %bb.42(0x80000000); %bb.42(100.00%)

  %74:gpr = LDRi12 %16:gpr, 20, 14, $noreg :: (load 4 from %ir.9)
  ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
  $r0 = COPY %14:gpr
  $r1 = COPY %74:gpr
  $r2 = COPY %7:gpr
  BL &memcpy, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit killed $r1, implicit killed $r2, implicit-def $sp, implicit-def dead $r0
  ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
  %95:gpr = COPY %7:gpr
  B %bb.42

bb.30.if.else45:
; predecessors: %bb.25
  successors: %bb.33(0x40000000), %bb.31(0x40000000); %bb.33(50.00%), %bb.31(50.00%)

  %46:gpr = ANDri %6:gprnopc, 240, 14, $noreg, $noreg
  CMPri %46:gpr, 240, 14, $noreg, implicit-def $cpsr
  Bcc %bb.33, 0, killed $cpsr
  B %bb.31

bb.31.lor.lhs.false:
; predecessors: %bb.30
  successors: %bb.32(0x40000000), %bb.33(0x40000000); %bb.32(50.00%), %bb.33(50.00%)

  %47:gprnopc = LDRBi12 %13:gpr, 12, 14, $noreg :: (load 1 from %ir.lastcmd, align 4)
  CMPrr %6:gprnopc, %47:gprnopc, 14, $noreg, implicit-def $cpsr
  Bcc %bb.33, 1, killed $cpsr
  B %bb.32

bb.32.lor.lhs.false52:
; predecessors: %bb.31
  successors: %bb.36(0x30000000), %bb.33(0x50000000); %bb.36(37.50%), %bb.33(62.50%)

  %48:gprnopc = LDRBi12 %13:gpr, 13, 14, $noreg :: (load 1 from %ir.nostat)
  CMPri %48:gprnopc, 0, 14, $noreg, implicit-def $cpsr
  Bcc %bb.36, 0, killed $cpsr
  B %bb.33

bb.33.if.then54:
; predecessors: %bb.30, %bb.31, %bb.32
  successors: %bb.35(0x40000000), %bb.34(0x40000000); %bb.35(50.00%), %bb.34(50.00%)

  STRBi12 %6:gprnopc, %13:gpr, 12, 14, $noreg :: (store 1 into %ir.lastcmd56, align 4)
  STRBi12 %6:gprnopc, %stack.1.xbuf, 0, 14, $noreg :: (store 1 into %ir.14)
  %57:gprnopc = MOVi32imm 3711
  %58:gprnopc = MOVi 1, 14, $noreg, $noreg
  TSTrsr %58:gprnopc, %57:gprnopc, %5:gprnopc, 3, 14, $noreg, implicit-def $cpsr
  Bcc %bb.35, 0, killed $cpsr
  B %bb.34

bb.34.if.then62:
; predecessors: %bb.33
  successors: %bb.35(0x80000000); %bb.35(100.00%)

  %59:gpr = LDRLIT_ga_pcrel @status_event
  %60:gpr = ADDrsi %59:gpr, %5:gprnopc, 34, 14, $noreg, $noreg
  %61:gpr = ADDri %stack.1.xbuf, 0, 14, $noreg, $noreg
  %62:gpr = nuw ADDri %61:gpr, 1, 14, $noreg, $noreg
  ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
  %63:gpr = LDRi12 %60:gpr, 12, 14, $noreg :: (load 4 from %ir.decode60)
  $r0 = COPY %16:gpr
  $r1 = COPY %62:gpr
  BLX %63:gpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit killed $r1, implicit-def $sp
  ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp

bb.35.if.end65:
; predecessors: %bb.33, %bb.34
  successors: %bb.39(0x80000000); %bb.39(100.00%)

  %64:gpr = LDRLIT_ga_pcrel @status_event
  %65:gpr = ADDrsi %64:gpr, %5:gprnopc, 34, 14, $noreg, $noreg
  %66:gpr = LDRi12 %65:gpr, 4, 14, $noreg :: (load 4 from %ir.qlen67)
  %8:gpr = nsw ADDri %66:gpr, 1, 14, $noreg, $noreg
  %93:gpr = COPY %8:gpr
  B %bb.39

bb.36.if.else69:
; predecessors: %bb.32
  successors: %bb.38(0x40000000), %bb.37(0x40000000); %bb.38(50.00%), %bb.37(50.00%)

  %49:gprnopc = MOVi32imm 3711
  %50:gprnopc = MOVi 1, 14, $noreg, $noreg
  TSTrsr %50:gprnopc, %49:gprnopc, %5:gprnopc, 3, 14, $noreg, implicit-def $cpsr
  Bcc %bb.38, 0, killed $cpsr
  B %bb.37

bb.37.if.then73:
; predecessors: %bb.36
  successors: %bb.38(0x80000000); %bb.38(100.00%)

  %51:gpr = LDRLIT_ga_pcrel @status_event
  %52:gpr = ADDrsi %51:gpr, %5:gprnopc, 34, 14, $noreg, $noreg
  ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
  %53:gpr = ADDri %stack.1.xbuf, 0, 14, $noreg, $noreg
  %54:gpr = LDRi12 %52:gpr, 12, 14, $noreg :: (load 4 from %ir.decode71)
  $r0 = COPY %16:gpr
  $r1 = COPY %53:gpr
  BLX %54:gpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit killed $r1, implicit-def $sp
  ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp

bb.38.if.end78:
; predecessors: %bb.36, %bb.37
  successors: %bb.39(0x80000000); %bb.39(100.00%)

  %55:gpr = LDRLIT_ga_pcrel @status_event
  %56:gpr = ADDrsi %55:gpr, %5:gprnopc, 34, 14, $noreg, $noreg
  %9:gpr = LDRi12 %56:gpr, 4, 14, $noreg :: (load 4 from %ir.qlen80)
  %93:gpr = COPY %9:gpr

bb.39.if.end81:
; predecessors: %bb.38, %bb.35
  successors: %bb.41(0x40000000), %bb.40(0x40000000); %bb.41(50.00%), %bb.40(50.00%)

  %10:gpr = COPY %93:gpr
  %67:gpr = MVNi 11, 14, $noreg, $noreg
  CMPrr %10:gpr, %15:gpr, 14, $noreg, implicit-def $cpsr
  %94:gpr = COPY %67:gpr
  Bcc %bb.41, 12, killed $cpsr
  B %bb.40

bb.40.if.end85:
; predecessors: %bb.39
  successors: %bb.41(0x80000000); %bb.41(100.00%)

  ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
  %68:gpr = ADDri %stack.1.xbuf, 0, 14, $noreg, $noreg
  $r0 = COPY %14:gpr
  $r1 = COPY %68:gpr
  $r2 = COPY %10:gpr
  BL &memcpy, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit killed $r1, implicit killed $r2, implicit-def $sp, implicit-def dead $r0
  ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
  %94:gpr = COPY %10:gpr

bb.41.cleanup:
; predecessors: %bb.39, %bb.40
  successors: %bb.42(0x80000000); %bb.42(100.00%)

  %11:gpr = COPY %94:gpr
  %95:gpr = COPY %11:gpr

bb.42.cleanup87:
; predecessors: %bb.1, %bb.41, %bb.26, %bb.29, %bb.28, %bb.44
  successors: %bb.43(0x7ffff800), %bb.5(0x00000800); %bb.43(100.00%), %bb.5(0.00%)

  %12:gpr = COPY %95:gpr
  %85:gpr = LDRi12 %21:gpr, 0, 14, $noreg :: (volatile load 4 from @__stack_chk_guard)
  %86:gpr = LDRi12 %stack.0.StackGuardSlot, 0, 14, $noreg :: (volatile load 4 from %stack.0.StackGuardSlot)
  dead %87:gpr = SUBrr %85:gpr, %86:gpr, 14, $noreg, def $cpsr
  Bcc %bb.5, 1, killed $cpsr
  B %bb.43

bb.43.cleanup87:
; predecessors: %bb.42

  $r0 = COPY %12:gpr
  BX_RET 14, $noreg, implicit killed $r0

# End machine code for function snd_midi_event_decode.

*** Bad machine code: Using an undefined physical register ***
- function:    snd_midi_event_decode
- basic block: %bb.6 if.then21 (0x803d008e0)
- instruction: TCRETURNri %79:tcgpr, implicit $sp, implicit $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3
- operand 2:   implicit $r0

*** Bad machine code: Using an undefined physical register ***
- function:    snd_midi_event_decode
- basic block: %bb.6 if.then21 (0x803d008e0)
- instruction: TCRETURNri %79:tcgpr, implicit $sp, implicit $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3
- operand 3:   implicit killed $r1

*** Bad machine code: Using an undefined physical register ***
- function:    snd_midi_event_decode
- basic block: %bb.6 if.then21 (0x803d008e0)
- instruction: TCRETURNri %79:tcgpr, implicit $sp, implicit $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3
- operand 4:   implicit killed $r2

*** Bad machine code: Using an undefined physical register ***
- function:    snd_midi_event_decode
- basic block: %bb.6 if.then21 (0x803d008e0)
- instruction: TCRETURNri %79:tcgpr, implicit $sp, implicit $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3
- operand 5:   implicit killed $r3
fatal error: error in backend: Found 4 machine code errors.
cc: error: clang frontend command failed with exit code 70 (use -v to see invocation)
FreeBSD clang version 8.0.0 (tags/RELEASE_800/final 356365) (based on LLVM 8.0.0)
Target: armv6-unknown-freebsd13.0-gnueabihf
Thread model: posix
InstalledDir: /usr/bin
Comment 1 Jan Beich freebsd_committer 2019-05-08 03:18:23 UTC
Created attachment 204254 [details]
command line args (for clang 8)
Comment 2 Jan Beich freebsd_committer 2019-05-08 03:20:31 UTC
armv7 and aarch64 are not affected. Can you minimize and report upstream?
Comment 3 Jan Beich freebsd_committer 2019-05-08 03:44:36 UTC
*** Bug 237784 has been marked as a duplicate of this bug. ***
Comment 5 commit-hook freebsd_committer 2019-05-08 05:45:52 UTC
A commit references this bug:

Author: dim
Date: Wed May  8 05:45:01 UTC 2019
New revision: 347243
URL: https://svnweb.freebsd.org/changeset/base/347243

Log:
  Pull in r360099 from upstream llvm trunk (by Eli Friedman):

    [ARM] Glue register copies to tail calls.

    This generally follows what other targets do. I don't completely
    understand why the special case for tail calls existed in the first
    place; even when the code was committed in r105413, call lowering
    didn't work in the way described in the comments.

    Stack protector lowering breaks if the register copies are not glued
    to a tail call: we have to insert the stack protector check before
    the tail call, and we choose the location based on the assumption
    that all physical register dependencies of a tail call are adjacent
    to the tail call. (See FindSplitPointForStackProtector.) This is sort
    of fragile, but I don't see any reason to break that assumption.

    I'm guessing nobody has seen this before just because it's hard to
    convince the scheduler to actually schedule the code in a way that
    breaks; even without the glue, the only computation that could
    actually be scheduled after the register copies is the computation of
    the call address, and the scheduler usually prefers to schedule that
    before the copies anyway.

    Fixes https://bugs.llvm.org/show_bug.cgi?id=41417

    Differential Revision: https://reviews.llvm.org/D60427

  This should fix several instances of "Bad machine code: Using an
  undefined physical register", when compiling ports such as
  multimedia/vlc, audio/alsa-lib and devel/avro-c for armv6, with
  -fstack-protector-strong.

  Reported by:	jbeich
  PR:		237074, 237783, 237784
  MFC after:	3 days

Changes:
  head/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp
Comment 6 Dimitry Andric freebsd_committer 2019-05-08 17:26:47 UTC

*** This bug has been marked as a duplicate of bug 237074 ***
Comment 7 commit-hook freebsd_committer 2019-05-11 09:57:28 UTC
A commit references this bug:

Author: dim
Date: Sat May 11 09:57:00 UTC 2019
New revision: 347486
URL: https://svnweb.freebsd.org/changeset/base/347486

Log:
  MFC r347243:

  Pull in r360099 from upstream llvm trunk (by Eli Friedman):

    [ARM] Glue register copies to tail calls.

    This generally follows what other targets do. I don't completely
    understand why the special case for tail calls existed in the first
    place; even when the code was committed in r105413, call lowering
    didn't work in the way described in the comments.

    Stack protector lowering breaks if the register copies are not glued
    to a tail call: we have to insert the stack protector check before
    the tail call, and we choose the location based on the assumption
    that all physical register dependencies of a tail call are adjacent
    to the tail call. (See FindSplitPointForStackProtector.) This is sort
    of fragile, but I don't see any reason to break that assumption.

    I'm guessing nobody has seen this before just because it's hard to
    convince the scheduler to actually schedule the code in a way that
    breaks; even without the glue, the only computation that could
    actually be scheduled after the register copies is the computation of
    the call address, and the scheduler usually prefers to schedule that
    before the copies anyway.

    Fixes https://bugs.llvm.org/show_bug.cgi?id=41417

    Differential Revision: https://reviews.llvm.org/D60427

  This should fix several instances of "Bad machine code: Using an
  undefined physical register", when compiling ports such as
  multimedia/vlc, audio/alsa-lib and devel/avro-c for armv6, with
  -fstack-protector-strong.

  Reported by:	jbeich
  PR:		237074, 237783, 237784

Changes:
_U  stable/11/
  stable/11/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp
_U  stable/12/
  stable/12/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp