The kernel driver for the Interrupt Translation Service of ARM's Generic Interrupt Controller version 3 (sys/arm64/arm64/gicv3_its.c) reads the GICR_TYPER memory-mapped register of the redistributor in its its_init_cpu() function:
/* Check if the ITS is enabled on this CPU */
if ((gic_r_read_4(gicv3, GICR_TYPER) & GICR_TYPER_PLPIS) == 0)
This is a 32-bit read. However, GICR_TYPER is a 64-bit register and the GICv3 specification (, §11.1.3) only requires that such accesses be supported on systems with at least one core supporting Aarch32. By contrast, 64-bit reads are always supported.
I suggest extending the read to 64 bits. By the way, the main GICv3 driver (sys/arm64/arm64/gic_v3.c) also reads GICR_TYPER, and it does so with bus_read_8().
This issue showed up on a software implementation of the ITS (hypervisor) that expected a 64-bit read.
A commit in branch main references this bug:
Author: Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2021-09-15 09:13:41 +0000
Commit: Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2021-09-15 09:13:41 +0000
Use a 64 bit read to access GICR_TYPER
The GICv3 ITS only needs to implement 32 bit access to the GICR_TYPER
when the CPU implements AArch32. As this may not always be the case
use a 64 bit read when checking if the ITS is enabled on the CPU.
Reported by: Olivier Delande <firstname.lastname@example.org>
Sponsored by: The FreeBSD Foundation
sys/arm64/arm64/gicv3_its.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)