Attachment #159354 for bug #201958

View | Details | Raw Unified | Return to bug 201958
Collapse All | Expand All

Lines 113-118 AR71XX_ENV_ROUTERBOOT opt_ar71xx.h Link Here

(-)b/sys/conf/options.mips (+7 lines)
113	AR71XX_ATH_EEPROM opt_ar71xx.h	113	AR71XX_ATH_EEPROM opt_ar71xx.h
114		114
115	#	115	#
		116	# Options that choose the Ralink RT model
		117	#
		118	RT3050F opt_global.h
		119	RT3052F opt_global.h
		120	RT5350F opt_global.h
		121
		122	#
116	# Options that control the Ralink RT305xF Etherenet MAC.	123	# Options that control the Ralink RT305xF Etherenet MAC.
117	#	124	#
118	IF_RT_DEBUG opt_if_rt.h	125	IF_RT_DEBUG opt_if_rt.h




# $FreeBSD$
# device.hints
hint.obio.0.at="nexus0"
hint.obio.0.maddr=0x10000000
hint.obio.0.msize=0x10000000

hint.nvram.0.sig=0xe5e60a74
hint.nvram.0.base=0x1f030000
hint.nvram.0.maxsize=0x2000
hint.nvram.0.flags=3 # 1 = No check, 2 = Format Generic
hint.nvram.1.sig=0x5a045e94
hint.nvram.1.base=0x1f032000
hint.nvram.1.maxsize=0x4000
hint.nvram.1.flags=3 # 1 = No check, 2 = Format Generic

# on-board Ralink Frame Engine
hint.rt.0.at="nexus0"
hint.rt.0.maddr=0x10100000
hint.rt.0.msize=0x10000
hint.rt.0.irq=3
# macaddr can be statically set
#hint.rt.0.macaddr="xx:xx:xx:xx:xx:xx"

# Settings for OLIMEX RT5350F-EVB
# Setups button as input in GPIO0, relays as output on GPIO12 and GPIO14
hint.gpio.0.function_set=0x1C
hint.gpio.0.pinmask=0x5001
hint.gpio.0.pinon=0x5000
hint.gpio.0.pinin=0x1

# on-board Ralink 2872 802.11n core
hint.rt2860.0.at="nexus0"
hint.rt2860.0.maddr=0x10180000
hint.rt2860.0.msize=0x40000
hint.rt2860.0.irq=4

hint.rt.0.phymask=0x1f
hint.rt.0.media=100
hint.rt.0.fduplex=1





#
# OLIMEX RT5350F: Boot from TFTP
#

include		"RT5350_BASE"
ident		"OLIMEX_RT5350"
hints		"OLIMEX_RT5350.hints"

device		md
device          geom_uzip
options         GEOM_UZIP

options         ROOTDEVNAME=\"ufs:md0.uzip\"

options         MD_ROOT
options         MD_ROOT_SIZE=6144




# RT305X -- Kernel configuration file for FreeBSD/mips for Ralink RT305xF systems
#
# For more information on this file, please read the handbook section on
# Kernel Configuration Files:
#
#    http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
#
# The handbook is also available locally in /usr/share/doc/handbook
# if you've installed the doc distribution, otherwise always see the
# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
# latest information.
#
# An exhaustive list of options and more detailed explanations of the
# device lines is also present in the ../../conf/NOTES and NOTES files. 
# If you are in doubt as to the purpose or necessity of a line, check first 
# in NOTES.
#
# $FreeBSD$

ident		RT5350

machine		mips mipsel
makeoptions	MIPS_LITTLE_ENDIAN=defined
makeoptions	KERNLOADADDR=0x80800000

# Don't build any modules yet.
makeoptions	MODULES_OVERRIDE="wlan_xauth wlan_wep wlan_tkip wlan_acl wlan_amrr wlan_ccmp wlan_rssadapt if_bridge bridgestp msdosfs md ipfw dummynet libalias geom/geom_label ufs usb/uplcom usb/u3g usb/umodem usb/umass usb/ucom cam zlib"
makeoptions	RT5350F

include		"../rt305x/std.rt5350"

hints		"RT5350_BASE.hints"		#Default places to look for devices.

#makeoptions	DEBUG=-g		#Build kernel with gdb(1) debug symbols

# Debugging for use in -current
#options 	DEADLKRES		#Enable the deadlock resolver
#options 	INVARIANTS		#Enable calls of extra sanity checking
#options 	INVARIANT_SUPPORT	#Extra sanity checks of internal structures, required by INVARIANTS
#options 	WITNESS			#Enable checks to detect deadlocks and cycles
#options 	WITNESS_SKIPSPIN	#Don't run witness on spinlocks for speed
#options         DIAGNOSTIC
#options     DEBUG_LOCKS
#options     DEBUG_VFS_LOCKS
#options 	GDB
options 	DDB
options 	KDB

options 	SCHED_ULE
options 	INET			#InterNETworking
options 	NFSCL			#Network Filesystem Client
options 	NFS_ROOT		#NFS usable as /, requires NFSCL
options 	PSEUDOFS		#Pseudo-filesystem framework
#options 	_KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions

options 	TMPFS			# TMP Memory Filesystem

options 	FFS			#Berkeley Fast Filesystem

# Options for making kernel less hangry
makeoptions	INLINE_LIMIT=1024
options 	MAXUSERS=3
options 	MAXFILES=512
options 	NSFBUFS=256
options 	SHMALL=128
options 	MSGBUF_SIZE=65536

# Options for making kernel smallest 
options 	NO_SYSCTL_DESCR		# No description string of sysctl
#options 	NO_FFS_SNAPSHOT		# Disable Snapshot supporting
options 	SCSI_NO_SENSE_STRINGS
options 	SCSI_NO_OP_STRINGS
options 	RWLOCK_NOINLINE
options 	SX_NOINLINE
options 	NO_SWAPPING
options         MROUTING                # Multicast routing
options 	IPFIREWALL_DEFAULT_TO_ACCEPT

device		random
device		loop
# RT3050F, RT3052F have only pseudo PHYs, so mii not required
device		rt

device		ether
device 		bpf			# Berkeley packet filter
device		vlan
#device		lagg
#device          if_bridge
device		uart
nodevice	uart_ns8250
device 		tun			# Packet tunnel.

device		wlan

device		gpio
device		gpioled

device		nvram2env

device		usb
options 	SCSI_DELAY=1000		# Delay (in ms) before probing SCSI

#options 	USB_EHCI_BIG_ENDIAN_DESC        # handle big-endian byte order
#options 	USB_DEBUG
#options 	USB_REQ_DEBUG




# $FreeBSD$
# device.hints
hint.obio.0.at="nexus0"
hint.obio.0.maddr=0x10000000
hint.obio.0.msize=0x10000000

hint.nvram.0.sig=0xe5e60a74
hint.nvram.0.base=0x1f030000
hint.nvram.0.maxsize=0x2000
hint.nvram.0.flags=3 # 1 = No check, 2 = Format Generic
hint.nvram.1.sig=0x5a045e94
hint.nvram.1.base=0x1f032000
hint.nvram.1.maxsize=0x4000
hint.nvram.1.flags=3 # 1 = No check, 2 = Format Generic

# on-board Ralink Frame Engine
hint.rt.0.at="nexus0"
hint.rt.0.maddr=0x10100000
hint.rt.0.msize=0x10000
hint.rt.0.irq=3
# macaddr can be statically set
#hint.rt.0.macaddr="xx:xx:xx:xx:xx:xx"

# on-board Ralink 2872 802.11n core
hint.rt2860.0.at="nexus0"
hint.rt2860.0.maddr=0x10180000
hint.rt2860.0.msize=0x40000
hint.rt2860.0.irq=4

hint.rt.0.phymask=0x1f
hint.rt.0.media=100
hint.rt.0.fduplex=1


Lines 248-256 obio_attach(device_t dev) Link Here

(-)b/sys/mips/rt305x/obio.c (+2 lines)
248	obio_add_res_child(dev, "uart", 1,	248	obio_add_res_child(dev, "uart", 1,
249	UARTLITE_BASE, (UARTLITE_END - UARTLITE_BASE + 1),	249	UARTLITE_BASE, (UARTLITE_END - UARTLITE_BASE + 1),
250	IC_UARTLITE);	250	IC_UARTLITE);
		251	#if defined(RT3050F) \|\| defined(RT3052F)
251	obio_add_res_child(dev, "cfi", 0,	252	obio_add_res_child(dev, "cfi", 0,
252	FLASH_BASE, (FLASH_END - FLASH_BASE + 1),	253	FLASH_BASE, (FLASH_END - FLASH_BASE + 1),
253	-1);	254	-1);
		255	#endif
254	obio_add_res_child(dev, "dotg", 0,	256	obio_add_res_child(dev, "dotg", 0,
255	USB_OTG_BASE, (USB_OTG_END - USB_OTG_BASE + 1),	257	USB_OTG_BASE, (USB_OTG_END - USB_OTG_BASE + 1),
256	IC_OTG);	258	IC_OTG);




/*-
 * Copyright (c) 2015, Emmanuel Vadot <manu@bidouilliste.com>
 * Copyright (c) 2010-2011, Aleksandr Rybalko <ray@ddteam.net>
 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
 * Copyright (c) 2009, Luiz Otavio O Souza.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without

 */

/*
 * GPIO driver for RT305X/RT5350 SoC.
 */

#include <sys/cdefs.h>

/*
 * Helpers
 */
static void rt305x_gpio_pin_configure(device_t dev, struct rt305x_gpio_softc *sc,
    struct gpio_pin *pin, uint32_t flags);

/*

static int rt305x_gpio_pin_toggle(device_t dev, uint32_t pin);

static void
rt305x_gpio_pin_configure(device_t dev, struct rt305x_gpio_softc *sc, struct gpio_pin *pin,
    unsigned int flags)
{
	GPIO_LOCK(sc);
	uint32_t reg;

	/*
	 * Manage input/output
	 */
	if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
		pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
		reg = bus_read_4(sc->gpio_mem_res, GPIO_REG(pin->gp_pin, DIR));
		if (flags & GPIO_PIN_OUTPUT) {
			pin->gp_flags |= GPIO_PIN_OUTPUT;
			reg |= GPIO_MASK(pin->gp_pin);
		}
		else {
			pin->gp_flags |= GPIO_PIN_INPUT;
			reg &= ~GPIO_MASK(pin->gp_pin);
		}
		bus_write_4(sc->gpio_mem_res, GPIO_REG(pin->gp_pin, DIR), reg);
		reg = bus_read_4(sc->gpio_mem_res, GPIO_REG(pin->gp_pin, DIR));
	}

	if (flags & GPIO_PIN_INVOUT) {

		pin->gp_flags |= GPIO_PIN_REPORT;
		GPIO_BIT_SET(sc, pin->gp_pin, RENA);
		GPIO_BIT_SET(sc, pin->gp_pin, FENA);
		device_printf(sc->dev, "Will report interrupt on pin %d\n",
		    pin->gp_pin);

	}

	if (i >= sc->gpio_npins)
		return (EINVAL);

	rt305x_gpio_pin_configure(dev, sc, &sc->gpio_pins[i], flags);

	return (0);
}



	GPIO_LOCK(sc);
	if (value)
		bus_write_4(sc->gpio_mem_res, GPIO_REG(pin, SET), GPIO_MASK(pin));
	else
		bus_write_4(sc->gpio_mem_res, GPIO_REG(pin, RESET), GPIO_MASK(pin));
	GPIO_UNLOCK(sc);

	return (0);

{
	struct rt305x_gpio_softc *sc = device_get_softc(dev);
	int i;
	uint32_t	data;

	for (i = 0; i < sc->gpio_npins; i++) {
		if (sc->gpio_pins[i].gp_pin == pin)

		return (EINVAL);

	GPIO_LOCK(sc);
	data = bus_read_4(sc->gpio_mem_res, GPIO_REG(pin, DATA));
	data >>= GPIO_BIT_SHIFT(pin);
	*val = data & 1;
	GPIO_UNLOCK(sc);

	return (0);

		return (EINVAL);

	GPIO_LOCK(sc);
	bus_write_4(sc->gpio_mem_res, GPIO_REG(pin, TOG), GPIO_MASK(pin));
	GPIO_UNLOCK(sc);

	return (0);

			 * if now reset is high, check how long
			 * and do reset if less than 2 seconds
			 */
			if ( reset_pin &&
			    (time_uptime - sc->reset_gpio_ontime) < 2 )
				shutdown_nice(0);


		if ( (((value & input) >> i) & 1) != sc->gpio_pins[i].gp_last )
		{
			/* !system=GPIO subsystem=pin7 type=PIN_HIGH period=3 */
			snprintf(notify , sizeof(notify ), "period=%d",
			    (uint32_t)time_uptime - sc->gpio_pins[i].gp_time);
			snprintf(pinname, sizeof(pinname), "pin%02d", i);
			devctl_notify("GPIO", pinname,
			    (((value & input) >> i) & 1)?"PIN_HIGH":"PIN_LOW",
			    notify);
			printf("GPIO[%s] %s %s\n", pinname,
			    (((value & input) >> i) & 1)?"PIN_HIGH":"PIN_LOW",
			    notify);
			sc->gpio_pins[i].gp_last = ((value & input) >> i) & 1;
			sc->gpio_pins[i].gp_time = time_uptime;

	return (0);
}

static uint64_t
rt305x_gpio_init(device_t dev)
{
	uint64_t avl = ~0ULL;
	uint32_t gmode = rt305x_sysctl_get(SYSCTL_GPIOMODE);
	if (!(gmode & SYSCTL_GPIOMODE_RGMII_GPIO_MODE))
		avl &= ~RGMII_GPIO_MODE_MASK;
	if (!(gmode & SYSCTL_GPIOMODE_SDRAM_GPIO_MODE))
		avl &= ~SDRAM_GPIO_MODE_MASK;
	if (!(gmode & SYSCTL_GPIOMODE_MDIO_GPIO_MODE))
		avl &= ~MDIO_GPIO_MODE_MASK;
	if (!(gmode & SYSCTL_GPIOMODE_JTAG_GPIO_MODE))
		avl &= ~JTAG_GPIO_MODE_MASK;
	if (!(gmode & SYSCTL_GPIOMODE_UARTL_GPIO_MODE))
		avl &= ~UARTL_GPIO_MODE_MASK;
	if (!(gmode & SYSCTL_GPIOMODE_SPI_GPIO_MODE))
		avl &= ~SPI_GPIO_MODE_MASK;
	if (!(gmode & SYSCTL_GPIOMODE_I2C_GPIO_MODE))
		avl &= ~I2C_GPIO_MODE_MASK;
	if ((gmode & SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO) != 
	    SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO)
		avl &= ~I2C_GPIO_MODE_MASK;
/* D-Link DAP-1350 Board have
 * MDIO_GPIO_MODE
 * UARTF_GPIO_MODE
 * SPI_GPIO_MODE
 * I2C_GPIO_MODE
 * So we have 
 * 00000001 10000000 01111111 11111110
*/
	return (avl);

}

#define DAP1350_RESET_GPIO	10

static int
rt305x_gpio_attach(device_t dev)
{
	struct rt305x_gpio_softc *sc = device_get_softc(dev);
	int i;
	uint32_t reg, mask, pinon, pinin;
	sc->reset_gpio = DAP1350_RESET_GPIO;

	KASSERT((device_get_unit(dev) == 0),
	    ("rt305x_gpio_gpio: Only one gpio module supported"));

		return (ENXIO);
	}

	if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
	    &sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
		device_printf(dev, "unable to allocate IRQ resource\n");
		rt305x_gpio_detach(dev);
		return (ENXIO);
	}

	if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,
	    /* rt305x_gpio_filter, */
	    rt305x_gpio_intr, NULL, sc, &sc->gpio_ih))) {
		device_printf(dev,

	}

	sc->dev = dev;
	rt305x_gpio_pin_max(dev, &sc->gpio_npins);

	/* Get the current function set */
	reg = rt305x_sysctl_get(SYSCTL_GPIOMODE);
	/* Enable function bits that are required */
	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
	    "function_set", &mask) == 0) {
		device_printf(dev, "function_set: 0x%x\n", mask);
		reg |= mask;
	}
	/* Disable function bits that are required */
	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
	    "function_clear", &mask) == 0) {
		device_printf(dev, "function_clear: 0x%x\n", mask);
		reg &= ~mask;
	}
	rt305x_sysctl_set(SYSCTL_GPIOMODE, reg);

	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
	    "pinmask", &mask) != 0)
		mask = 0;
	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
	    "pinon", &pinon) != 0)
		pinon = 0;
	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
	    "pinin", &pinin) != 0)
		pinin = 0;
	device_printf(dev, "gpio pinmask=0x%x\n", mask);

	/* Configure all pins, keep the loader settings */
	reg = bus_read_4(sc->gpio_mem_res, GPIO_REG(22, DIR)) << GPIO_BIT_SHIFT(22);
	reg |= bus_read_4(sc->gpio_mem_res, GPIO_REG(0, DIR));
	for (i = 0; i < sc->gpio_npins; i++) {
		if ((mask & (1 << i)) == 0)
			continue;
		snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
		    "pin %d", i);
 		sc->gpio_pins[i].gp_pin = i;
 		sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
 		sc->gpio_pins[i].gp_flags = (reg & (1 << i)) ? GPIO_PIN_OUTPUT : GPIO_PIN_INPUT;
	}

	/* Turn on the hinted pins or configure them as inputs. */
	for (i = 0; i < sc->gpio_npins; i++) {
		if ((pinon & (1 << sc->gpio_pins[i].gp_pin)) != 0) {
			rt305x_gpio_pin_setflags(dev, sc->gpio_pins[i].gp_pin, GPIO_PIN_OUTPUT);
			rt305x_gpio_pin_set(dev, sc->gpio_pins[i].gp_pin, 1);
		}
		if ((pinin & (1 << sc->gpio_pins[i].gp_pin)) != 0)
			rt305x_gpio_pin_setflags(dev, sc->gpio_pins[i].gp_pin, GPIO_PIN_INPUT);
	}

	/* Setup reset pin interrupt */
	sc->reset_gpio = -1;
	if (TUNABLE_INT_FETCH("reset_gpio", &sc->reset_gpio)) {
		device_printf(dev, "\tHinted reset_gpio %d\n", sc->reset_gpio);
	}
#ifdef	notyet
	if (sc->reset_gpio != -1) {
		rt305x_gpio_pin_setflags(dev, sc->reset_gpio,
		    GPIO_PIN_INPUT|GPIO_PIN_INVOUT|
		    GPIO_PIN_INVOUT|GPIO_PIN_REPORT);
		device_printf(dev, "\tUse reset_gpio %d\n", sc->reset_gpio);
	}
#else
	if (sc->reset_gpio != -1) {
		rt305x_gpio_pin_setflags(dev, sc->reset_gpio,
		    GPIO_PIN_INPUT|GPIO_PIN_INVOUT);
		device_printf(dev, "\tUse reset_gpio %d\n", sc->reset_gpio);
	}

};
static devclass_t rt305x_gpio_devclass;

DRIVER_MODULE(rt305x_gpio, obio, rt305x_gpio_driver,
    rt305x_gpio_devclass, 0, 0);




/*-
 * Copyright (c) 2015, Emmanuel Vadot <manu@bidouilliste.com>
 * Copyright (c) 2010 Aleksandr Rybalko.
 * All rights reserved.
 *

#ifndef _RT305X_GPIO_H_
#define _RT305X_GPIO_H_

#define NGPIO			52

#define RGMII_GPIO_MODE_MASK	(0x0fffULL<<40)
#define SDRAM_GPIO_MODE_MASK  	(0xffffULL<<24)
#define MDIO_GPIO_MODE_MASK   	(0x0003ULL<<22)
#define JTAG_GPIO_MODE_MASK   	(0x001fULL<<17)
#define UARTL_GPIO_MODE_MASK  	(0x0003ULL<<15)
#define UARTF_GPIO_MODE_MASK  	(0x00ffULL<<7)
#define SPI_GPIO_MODE_MASK    	(0x000fULL<<3)
#define I2C_GPIO_MODE_MASK    	(0x0003ULL<<1)

#if defined(RT3050F) || defined(RT3052F)
#define NGPIO			52

#define RGMII_GPIO_MODE_MASK	(0x0fffULL<<40)
#define SDRAM_GPIO_MODE_MASK  	(0xffffULL<<24)
#define MDIO_GPIO_MODE_MASK   	(0x0003ULL<<22)

#define GPIO23_00_INT		0x00 /* Programmed I/O Int Status */
#define GPIO23_00_EDGE		0x04 /* Programmed I/O Edge Status */
#define GPIO23_00_RENA		0x08 /* Programmed I/O Int on Rising */

	((g<24)?(1<<g):(g<40)?(1<<(g-24)):(1<<(g-40)))
#define GPIO_BIT_SHIFT(g)	((g<24)?(g):(g<40)?(g-24):(g-40))

#define GPIO_READ(r, g, n) 						\
	bus_read_4(r->gpio_mem_res, GPIO_REG(g, n))
#define GPIO_WRITE(r, g, n, v) 						\
	bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), v)
#define GPIO_READ_ALL(r, n) 						\
	(((uint64_t)bus_read_4(r->gpio_mem_res, GPIO23_00_##n)) |	\
	(((uint64_t)bus_read_4(r->gpio_mem_res, GPIO39_24_##n)) << 24) |\

	bus_write_4(r->gpio_mem_res, GPIO39_24_##n, (v>>24)&0x0000ffff);\
	bus_write_4(r->gpio_mem_res, GPIO51_40_##n, (v>>40)&0x00000fff);}

#endif

#ifdef RT5350F
#define NGPIO			28

#define SPI_CS1_GPIO_MODE_MASK		(0x0001ULL<<27)
#define PHY_LED_GPIO_MODE_MASK   	(0x0003ULL<<22)

#define GPIO21_00_INT		0x00 /* Programmed I/O Int Status */
#define GPIO21_00_EDGE		0x04 /* Programmed I/O Edge Status */
#define GPIO21_00_RENA		0x08 /* Programmed I/O Int on Rising */
#define GPIO21_00_FENA		0x0C /* Programmed I/O Int on Falling */
#define GPIO21_00_DATA		0x20 /* Programmed I/O Data */
#define GPIO21_00_DIR		0x24 /* Programmed I/O Direction */
#define GPIO21_00_POL		0x28 /* Programmed I/O Pin Polarity */
#define GPIO21_00_SET		0x2C /* Set PIO Data Bit */
#define GPIO21_00_RESET		0x30 /* Clear PIO Data bit */
#define GPIO21_00_TOG		0x34 /* Toggle PIO Data bit */

#define GPIO27_22_INT		0x60
#define GPIO27_22_EDGE		0x64
#define GPIO27_22_RENA		0x68
#define GPIO27_22_FENA		0x6C
#define GPIO27_22_DATA		0x70
#define GPIO27_22_DIR		0x74
#define GPIO27_22_POL		0x78
#define GPIO27_22_SET		0x7C
#define GPIO27_22_RESET		0x80
#define GPIO27_22_TOG		0x84

#define GPIO_REG(g, n)							\
	((g < 22) ? (GPIO21_00_##n) : (GPIO27_22_##n))

#define GPIO_MASK(g)					\
	((g < 22) ? (1UL << g ) : (1UL << (g - 22)))

#define GPIO_BIT_SHIFT(g)	(g < 22) ? (g) : (g - 22)

#define GPIO_READ_ALL(r, n) 						\
	(((uint64_t)bus_read_4(r->gpio_mem_res, GPIO21_00_##n)) |	\
	(((uint64_t)bus_read_4(r->gpio_mem_res, GPIO27_22_##n)) << 22))
#define GPIO_WRITE_ALL(r, n, v) 					\
	{bus_write_4(r->gpio_mem_res,GPIO21_00_##n, v      &0x00ffffff);\
	bus_write_4(r->gpio_mem_res, GPIO27_22_##n, (v>>22)&0x0000ffff);}

#endif


#define GPIO_READ(r, g, n) 						\
	bus_read_4(r->gpio_mem_res, GPIO_REG(g, n))
#define GPIO_WRITE(r, g, n, v) 						\
	bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), v)

#define GPIO_BIT_CLR(r, g, n) 						\
	bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), 			\

	    bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) | GPIO_MASK(g))

#define GPIO_BIT_GET(r, g, n)						\
  ((bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) >>	\
    GPIO_BIT_SHIFT(g)) & 1)

#define GPIO_LOCK(_sc)		mtx_lock(&(_sc)->gpio_mtx)
#define GPIO_UNLOCK(_sc)	mtx_unlock(&(_sc)->gpio_mtx)

Lines 1-4 Link Here

(-)b/sys/mips/rt305x/rt305x_sysctl.c (+3 lines)
1	/*-	1	/*-
		2	* Copyright (c) 2015, Emmanuel Vadot <manu@bidouilliste.com>
2	* Copyright (c) 2010 Aleksandr Rybalko.	3	* Copyright (c) 2010 Aleksandr Rybalko.
3	* All rights reserved.	4	* All rights reserved.
4	*	5	*
Lines 70-75 rt305x_sysctl_dump_config(device_t dev) Link Here
70	(val >> 24) & 0xff);	71	(val >> 24) & 0xff);
71		72
72	DUMPREG(SYSCTL_SYSCFG);	73	DUMPREG(SYSCTL_SYSCFG);
		74	#if defined(RT3050F) \|\| defined(RT3052F)
73	if ( val & SYSCTL_SYSCFG_INIC_EE_SDRAM)	75	if ( val & SYSCTL_SYSCFG_INIC_EE_SDRAM)
74	printf("\tGet SDRAM config from EEPROM\n");	76	printf("\tGet SDRAM config from EEPROM\n");
75	if ( val & SYSCTL_SYSCFG_INIC_8MB_SDRAM)	77	if ( val & SYSCTL_SYSCFG_INIC_8MB_SDRAM)
Lines 124-129 rt305x_sysctl_dump_config(device_t dev) Link Here
124	SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT));	126	SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT));
125	DUMPREG(SYSCTL_GPIOMODE);	127	DUMPREG(SYSCTL_GPIOMODE);
126	#undef DUMPREG	128	#undef DUMPREG
		129	#endif
127		130
128	return;	131	return;
129	}	132	}




/*-
 * Copyright (c) 2015, Emmanuel Vadot <manu@bidouilliste.com>
 * Copyright (c) 2010 Aleksandr Rybalko.
 * All rights reserved.
 *

#ifndef _RT305XREG_H_
#define _RT305XREG_H_

/* XXX: must move to config */
#define RT305X		1
#define RT305XF		1
#define RT3052F		1
#define __U_BOOT__	1
/* XXX: must move to config */

#ifdef RT3052F
#define PLATFORM_COUNTER_FREQ	(384 * 1000 * 1000)
#endif
#ifdef RT3050F
#define PLATFORM_COUNTER_FREQ	(320 * 1000 * 1000)
#endif
#ifdef RT5350F
#define PLATFORM_COUNTER_FREQ	(360 * 1000 * 1000)
#endif
#ifndef PLATFORM_COUNTER_FREQ
#error "Nor RT3052F nor RT3050F defined"
#endif

#define INTCTL_END 	0x100002FF
#define MEMCTRL_BASE	0x10000300
#define MEMCTRL_END 	0x100003FF /* SDRAM & Flash/SRAM */
#if defined(RT3050F) || defined(RT3052F)
#define PCM_BASE 	0x10000400
#define PCM_END 	0x100004FF
#endif
#define UART_BASE 	0x10000500
#define UART_END 	0x100005FF
#define PIO_BASE 	0x10000600
#define PIO_END 	0x100006FF
#if defined(RT3050F) || defined(RT3052F)
#define GDMA_BASE 	0x10000700
#define GDMA_END 	0x100007FF /* Generic DMA */
#define NANDFC_BASE 	0x10000800
#define NANDFC_END 	0x100008FF /* NAND Flash Controller */
#endif
#define I2C_BASE 	0x10000900
#define I2C_END 	0x100009FF
#define I2S_BASE 	0x10000A00

#define ETHSW_END 	0x10117FFF /* Ethernet Switch */
#define ROM_BASE 	0x10118000
#define ROM_END 	0x10119FFF
#ifdef RT5350F
#define USB_OTG_BASE	0x10120000
#define USB_OTG_END	0x1012FFFF
#endif
#define WLAN_BASE 	0x10180000
#define WLAN_END 	0x101BFFFF /* 802.11n MAC/BBP */
#if defined(RT3050F) || defined(RT3052F)
#define USB_OTG_BASE	0x101C0000
#define USB_OTG_END 	0x101FFFFF
#endif
#define EMEM_BASE 	0x1B000000
#define EMEM_END 	0x1BFFFFFF /* External SRAM/Flash */
#ifdef RT5350F
#define BOOT_ROM_BASE	0x1C000000
#define BOOT_ROM_END	0x1C003FFF
#endif
#if defined(RT3050F) || defined(RT3052F)
#define FLASH_BASE 	0x1F000000
#define FLASH_END 	0x1FFFFFFF /* Flash window */
#endif

#define OBIO_MEM_BASE	SYSCTL_BASE
#define OBIO_MEM_START	OBIO_MEM_BASE
#if defined(RT3050F) || defined(RT2052F)
#define OBIO_MEM_END	FLASH_END
#endif
#ifdef RT5350F
#define OBIO_MEM_END	BOOT_ROM_END
#endif

/* System Control */
#define SYSCTL_CHIPID0_3 	0x00 /* 'R''T''3''0' for RT305X or 'R' 'T' '5' '3' for RT5350 */
#define SYSCTL_CHIPID4_7 	0x04 /* '5''2'' '' ' for RT305X or '5' '0' ' ' ' ' for RT5350 */
#ifdef RT5350F
#define SYSCTL_REVID		0x0C /* 0x1 0x1 - */ 
#endif

#define SYSCTL_SYSCFG		0x10
#if defined(RT3050F) || defined(RT3052F)
#define SYSCTL_SYSCFG_INIC_EE_SDRAM		(1<<29)
#define SYSCTL_SYSCFG_INIC_8MB_SDRAM		(1<<28) 
#define SYSCTL_SYSCFG_GE0_MODE_MASK		0x03000000

#define SYSCTL_SYSCFG_SRAM_CS_MODE_WDOG_RST	1
#define SYSCTL_SYSCFG_SRAM_CS_MODE_BT_COEX	2
#define SYSCTL_SYSCFG_SDRAM_CLK_DRV		(1<<0) /* 8mA/12mA */
#endif
#ifdef RT5350F
#define SYSCTL_SYSCFG_PULL_EN			(1<<26)
#define SYSCTL_SYSCFG_SDR_PAD_DRV_MASK		0x0700000
#define SYSCTL_SYSCFG_SDR_PAD_DRV_SHIFT		20
#define SYSCTL_SYSCFG_SDR_PAD_DRV_0		0
#define SYSCTL_SYSCFG_SDR_PAD_DRV_1		1
#define SYSCTL_SYSCFG_SDR_PAD_DRV_2		2
#define SYSCTL_SYSCFG_USB0_MODE			(1<<10) /* 0 device / 1 host */
#define SYSCTL_SYSCFG_USB_PHY_EN		(1<<9)
#endif

#define SYSCTL_TESTSTAT		0x18
#define SYSCTL_TESTSTAT2	0x1C

#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_3NS_DELAY		3

#define SYSCTL_CLKCFG1		0x30
#if defined(RT3050F) || defined(RT3052F)
#define SYSCTL_CLKCFG1_PBUS_DIV_CLK_BY2		(1<<30)
#define SYSCTL_CLKCFG1_OTG_CLK_EN		(1<<18)
#define SYSCTL_CLKCFG1_I2S_CLK_EN		(1<<15)

#define SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT 		(1<<6)
#define SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK 		0x0000003f
#define SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT 	0
#endif
#ifdef RT5350F
#define SYSCTL_CLKCFG1_SYSTICK_EN		(1<<29)
#define SYSCTL_CLKCFG1_PDMA_CSR_CLK_GATE_BYP	(1<<23)
#define SYSCTL_CLKCFG1_UPHY0_CLK_EN		(1<<18)
#endif

#define SYSCTL_RSTCTRL		0x34
#define SYSCTL_RSTCTRL_ETHSW		(1<<23)

#define SYSCTL_RSTSTAT_SWSYSRST		(1<<2)
#define SYSCTL_RSTSTAT_WDRST		(1<<1)

#ifdef RT5350F
#define SYSCTL_CPU_SYS_CLKCFG	0x3C

#define SYSCTL_CLK_LUT_CFG	0x40

#define SYSCTL_CPU_CLK_AUTO_CFG	0x44

#define SYSCTL_CPU_PLL_DYN_CFG	0x48

#define SYSCTL_RF_RX_SD_CFG	0x58

#endif

#define SYSCTL_GPIOMODE		0x60
#if defined(RT3050F) || defined(RT3052F)
#define SYSCTL_GPIOMODE_RGMII_GPIO_MODE		(1<<9)
#define SYSCTL_GPIOMODE_SDRAM_GPIO_MODE  	(1<<8)
#define SYSCTL_GPIOMODE_MDIO_GPIO_MODE   	(1<<7)
#endif
#define SYSCTL_GPIOMODE_JTAG_GPIO_MODE   	(1<<6)
#define SYSCTL_GPIOMODE_UARTL_GPIO_MODE  	(1<<5)
#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_UARTF		(0<<2)

#define SYSCTL_GPIOMODE_SPI_GPIO_MODE    	(1<<1)
#define SYSCTL_GPIOMODE_I2C_GPIO_MODE    	(1<<0)

#if defined(RT3050F) || defined(RT3052F)
#define SYSCTL_MEMO0		0x68
#define SYSCTL_MEMO1		0x6C
#endif


/* Timer */
#define TIMER_TMRSTAT		0x00

#define IC_INT_ENA		0x34
#define IC_INT_DIS		0x38

#define IC_UDEV		19
#define IC_OTG		18
#define IC_ETHSW	17
#define IC_UARTLITE	12
#define IC_I2S		10
#define IC_PERFC	9
#if defined(RT3050F) || defined(RT2052)
#define IC_NAND		8
#endif
#define IC_DMA		7
#define IC_PIO		6
#define IC_UART		5

#define IC_SYSCTL	0

#define IC_LINE_GLOBAL		(1<<31) /* Only for DIS/ENA regs */
#ifdef RT5350F
#define IC_LINE_UDEV		(1<<19)
#endif
#define IC_LINE_OTG		(1<<18)
#define IC_LINE_ETHSW		(1<<17)
#define IC_LINE_UARTLITE	(1<<12)

#define IC_LINE_TIMER0		(1<<1)
#define IC_LINE_SYSCTL		(1<<0)

#define IC_INT_MASK		0x000717ff

/* GPIO */

#define GPIO23_00_INT		0x00 /* Programmed I/O Int Status */
#define GPIO23_00_EDGE		0x04 /* Programmed I/O Edge Status */
#define GPIO23_00_RENA		0x08 /* Programmed I/O Int on Rising */
#define GPIO23_00_FENA		0x0C /* Programmed I/O Int on Falling */
#define GPIO23_00_DATA		0x20 /* Programmed I/O Data */
#define GPIO23_00_DIR		0x24 /* Programmed I/O Direction */
#define GPIO23_00_POL		0x28 /* Programmed I/O Pin Polarity */
#define GPIO23_00_SET		0x2C /* Set PIO Data Bit */
#define GPIO23_00_RESET		0x30 /* Clear PIO Data bit */
#define GPIO23_00_TOG		0x34 /* Toggle PIO Data bit */

#define GPIO39_24_INT		0x38
#define GPIO39_24_EDGE		0x3c
#define GPIO39_24_RENA		0x40
#define GPIO39_24_FENA		0x44
#define GPIO39_24_DATA		0x48
#define GPIO39_24_DIR		0x4c
#define GPIO39_24_POL		0x50
#define GPIO39_24_SET		0x54
#define GPIO39_24_RESET		0x58
#define GPIO39_24_TOG		0x5c

#define GPIO51_40_INT		0x60
#define GPIO51_40_EDGE		0x64
#define GPIO51_40_RENA		0x68
#define GPIO51_40_FENA		0x6C
#define GPIO51_40_DATA		0x70
#define GPIO51_40_DIR		0x74
#define GPIO51_40_POL		0x78
#define GPIO51_40_SET		0x7C
#define GPIO51_40_RESET		0x80
#define GPIO51_40_TOG		0x84




#define GDMA_CHANNEL_REQ0	0
#define GDMA_CHANNEL_REQ1	1 /* (NAND-flash) */

Lines 5-7 files "../rt305x/files.rt305x" Link Here

(-)b/sys/mips/rt305x/std.rt305x (+1 lines)
5		5
6	cpu CPU_MIPS4KC	6	cpu CPU_MIPS4KC
7		7
		8	options RT3050

Added Link Here

(-)b/sys/mips/rt305x/std.rt5350 (+8 lines)
1	# $FreeBSD$
2	# Standard include file for RT5350 SoC
3
4	files "../rt305x/files.rt305x"
5
6	cpu CPU_MIPS4KC
7
8	options RT5350F

Return to bug 201958

Added Link Here

(-)b/sys/mips/conf/OLIMEX_RT5350.hints (+40 lines)
1	# $FreeBSD$
2	# device.hints
3	hint.obio.0.at="nexus0"
4	hint.obio.0.maddr=0x10000000
5	hint.obio.0.msize=0x10000000
6
7	hint.nvram.0.sig=0xe5e60a74
8	hint.nvram.0.base=0x1f030000
9	hint.nvram.0.maxsize=0x2000
10	hint.nvram.0.flags=3 # 1 = No check, 2 = Format Generic
11	hint.nvram.1.sig=0x5a045e94
12	hint.nvram.1.base=0x1f032000
13	hint.nvram.1.maxsize=0x4000
14	hint.nvram.1.flags=3 # 1 = No check, 2 = Format Generic
15
16	# on-board Ralink Frame Engine
17	hint.rt.0.at="nexus0"
18	hint.rt.0.maddr=0x10100000
19	hint.rt.0.msize=0x10000
20	hint.rt.0.irq=3
21	# macaddr can be statically set
22	#hint.rt.0.macaddr="xx:xx:xx:xx:xx:xx"
23
24	# Settings for OLIMEX RT5350F-EVB
25	# Setups button as input in GPIO0, relays as output on GPIO12 and GPIO14
26	hint.gpio.0.function_set=0x1C
27	hint.gpio.0.pinmask=0x5001
28	hint.gpio.0.pinon=0x5000
29	hint.gpio.0.pinin=0x1
30
31	# on-board Ralink 2872 802.11n core
32	hint.rt2860.0.at="nexus0"
33	hint.rt2860.0.maddr=0x10180000
34	hint.rt2860.0.msize=0x40000
35	hint.rt2860.0.irq=4
36
37	hint.rt.0.phymask=0x1f
38	hint.rt.0.media=100
39	hint.rt.0.fduplex=1
40

Added Link Here

(-)b/sys/mips/conf/OLIMEX_RT5350_MFS (+16 lines)
1	#
2	# OLIMEX RT5350F: Boot from TFTP
3	#
4
5	include "RT5350_BASE"
6	ident "OLIMEX_RT5350"
7	hints "OLIMEX_RT5350.hints"
8
9	device md
10	device geom_uzip
11	options GEOM_UZIP
12
13	options ROOTDEVNAME=\"ufs:md0.uzip\"
14
15	options MD_ROOT
16	options MD_ROOT_SIZE=6144

Added Link Here

(-)b/sys/mips/conf/RT5350_BASE (+105 lines)
1	# RT305X -- Kernel configuration file for FreeBSD/mips for Ralink RT305xF systems
2	#
3	# For more information on this file, please read the handbook section on
4	# Kernel Configuration Files:
5	#
6	# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
7	#
8	# The handbook is also available locally in /usr/share/doc/handbook
9	# if you've installed the doc distribution, otherwise always see the
10	# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
11	# latest information.
12	#
13	# An exhaustive list of options and more detailed explanations of the
14	# device lines is also present in the ../../conf/NOTES and NOTES files.
15	# If you are in doubt as to the purpose or necessity of a line, check first
16	# in NOTES.
17	#
18	# $FreeBSD$
19
20	ident RT5350
21
22	machine mips mipsel
23	makeoptions MIPS_LITTLE_ENDIAN=defined
24	makeoptions KERNLOADADDR=0x80800000
25
26	# Don't build any modules yet.
27	makeoptions MODULES_OVERRIDE="wlan_xauth wlan_wep wlan_tkip wlan_acl wlan_amrr wlan_ccmp wlan_rssadapt if_bridge bridgestp msdosfs md ipfw dummynet libalias geom/geom_label ufs usb/uplcom usb/u3g usb/umodem usb/umass usb/ucom cam zlib"
28	makeoptions RT5350F
29
30	include "../rt305x/std.rt5350"
31
32	hints "RT5350_BASE.hints" #Default places to look for devices.
33
34	#makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
35
36	# Debugging for use in -current
37	#options DEADLKRES #Enable the deadlock resolver
38	#options INVARIANTS #Enable calls of extra sanity checking
39	#options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
40	#options WITNESS #Enable checks to detect deadlocks and cycles
41	#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
42	#options DIAGNOSTIC
43	#options DEBUG_LOCKS
44	#options DEBUG_VFS_LOCKS
45	#options GDB
46	options DDB
47	options KDB
48
49	options SCHED_ULE
50	options INET #InterNETworking
51	options NFSCL #Network Filesystem Client
52	options NFS_ROOT #NFS usable as /, requires NFSCL
53	options PSEUDOFS #Pseudo-filesystem framework
54	#options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
55
56	options TMPFS # TMP Memory Filesystem
57
58	options FFS #Berkeley Fast Filesystem
59
60	# Options for making kernel less hangry
61	makeoptions INLINE_LIMIT=1024
62	options MAXUSERS=3
63	options MAXFILES=512
64	options NSFBUFS=256
65	options SHMALL=128
66	options MSGBUF_SIZE=65536
67
68	# Options for making kernel smallest
69	options NO_SYSCTL_DESCR # No description string of sysctl
70	#options NO_FFS_SNAPSHOT # Disable Snapshot supporting
71	options SCSI_NO_SENSE_STRINGS
72	options SCSI_NO_OP_STRINGS
73	options RWLOCK_NOINLINE
74	options SX_NOINLINE
75	options NO_SWAPPING
76	options MROUTING # Multicast routing
77	options IPFIREWALL_DEFAULT_TO_ACCEPT
78
79	device random
80	device loop
81	# RT3050F, RT3052F have only pseudo PHYs, so mii not required
82	device rt
83
84	device ether
85	device bpf # Berkeley packet filter
86	device vlan
87	#device lagg
88	#device if_bridge
89	device uart
90	nodevice uart_ns8250
91	device tun # Packet tunnel.
92
93	device wlan
94
95	device gpio
96	device gpioled
97
98	device nvram2env
99
100	device usb
101	options SCSI_DELAY=1000 # Delay (in ms) before probing SCSI
102
103	#options USB_EHCI_BIG_ENDIAN_DESC # handle big-endian byte order
104	#options USB_DEBUG
105	#options USB_REQ_DEBUG

Added Link Here

(-)b/sys/mips/conf/RT5350_BASE.hints (+33 lines)
1	# $FreeBSD$
2	# device.hints
3	hint.obio.0.at="nexus0"
4	hint.obio.0.maddr=0x10000000
5	hint.obio.0.msize=0x10000000
6
7	hint.nvram.0.sig=0xe5e60a74
8	hint.nvram.0.base=0x1f030000
9	hint.nvram.0.maxsize=0x2000
10	hint.nvram.0.flags=3 # 1 = No check, 2 = Format Generic
11	hint.nvram.1.sig=0x5a045e94
12	hint.nvram.1.base=0x1f032000
13	hint.nvram.1.maxsize=0x4000
14	hint.nvram.1.flags=3 # 1 = No check, 2 = Format Generic
15
16	# on-board Ralink Frame Engine
17	hint.rt.0.at="nexus0"
18	hint.rt.0.maddr=0x10100000
19	hint.rt.0.msize=0x10000
20	hint.rt.0.irq=3
21	# macaddr can be statically set
22	#hint.rt.0.macaddr="xx:xx:xx:xx:xx:xx"
23
24	# on-board Ralink 2872 802.11n core
25	hint.rt2860.0.at="nexus0"
26	hint.rt2860.0.maddr=0x10180000
27	hint.rt2860.0.msize=0x40000
28	hint.rt2860.0.irq=4
29
30	hint.rt.0.phymask=0x1f
31	hint.rt.0.media=100
32	hint.rt.0.fduplex=1
33

Lines 1-7 Link Here

(-)b/sys/mips/rt305x/rt305x_gpio.c (-72 / +82 lines)
1	/*-	1	/*-
		2	* Copyright (c) 2015, Emmanuel Vadot <manu@bidouilliste.com>
2	* Copyright (c) 2010-2011, Aleksandr Rybalko <ray@ddteam.net>	3	* Copyright (c) 2010-2011, Aleksandr Rybalko <ray@ddteam.net>
3	* Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>	4	* Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
4	* Copyright (c) 2009, Luiz Otavio O Souza.	5	* Copyright (c) 2009, Luiz Otavio O Souza.
5	* All rights reserved.	6	* All rights reserved.
6	*	7	*
7	* Redistribution and use in source and binary forms, with or without	8	* Redistribution and use in source and binary forms, with or without
Lines 28-34 Link Here
28	*/	29	*/
29		30
30	/*	31	/*
31	* GPIO driver for RT305X SoC.	32	* GPIO driver for RT305X/RT5350 SoC.
32	*/	33	*/
33		34
34	#include <sys/cdefs.h>	35	#include <sys/cdefs.h>
Lines 66-72 __FBSDID("$FreeBSD$"); Link Here
66	/*	67	/*
67	* Helpers	68	* Helpers
68	*/	69	*/
69	static void rt305x_gpio_pin_configure(struct rt305x_gpio_softc *sc,	70	static void rt305x_gpio_pin_configure(device_t dev, struct rt305x_gpio_softc *sc,
70	struct gpio_pin *pin, uint32_t flags);	71	struct gpio_pin *pin, uint32_t flags);
71		72
72	/*	73	/*
Lines 97-120 static int rt305x_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val); Link Here
97	static int rt305x_gpio_pin_toggle(device_t dev, uint32_t pin);	98	static int rt305x_gpio_pin_toggle(device_t dev, uint32_t pin);
98		99
99	static void	100	static void
100	rt305x_gpio_pin_configure(struct rt305x_gpio_softc sc, struct gpio_pin pin,	101	rt305x_gpio_pin_configure(device_t dev, struct rt305x_gpio_softc sc, struct gpio_pin pin,
101	unsigned int flags)	102	unsigned int flags)
102	{	103	{
103	GPIO_LOCK(sc);	104	GPIO_LOCK(sc);
		105	uint32_t reg;
104		106
105	/*	107	/*
106	* Manage input/output	108	* Manage input/output
107	*/	109	*/
108	if (flags & (GPIO_PIN_INPUT\|GPIO_PIN_OUTPUT)) {	110	if (flags & (GPIO_PIN_INPUT\|GPIO_PIN_OUTPUT)) {
109	pin->gp_flags &= ~(GPIO_PIN_INPUT\|GPIO_PIN_OUTPUT);	111	pin->gp_flags &= ~(GPIO_PIN_INPUT\|GPIO_PIN_OUTPUT);
		112	reg = bus_read_4(sc->gpio_mem_res, GPIO_REG(pin->gp_pin, DIR));
110	if (flags & GPIO_PIN_OUTPUT) {	113	if (flags & GPIO_PIN_OUTPUT) {
111	pin->gp_flags \|= GPIO_PIN_OUTPUT;	114	pin->gp_flags \|= GPIO_PIN_OUTPUT;
112	GPIO_BIT_SET(sc, pin->gp_pin, DIR);	115	reg \|= GPIO_MASK(pin->gp_pin);
113	}	116	}
114	else {	117	else {
115	pin->gp_flags \|= GPIO_PIN_INPUT;	118	pin->gp_flags \|= GPIO_PIN_INPUT;
116	GPIO_BIT_CLR(sc, pin->gp_pin, DIR);	119	reg &= ~GPIO_MASK(pin->gp_pin);
117	}	120	}
		121	bus_write_4(sc->gpio_mem_res, GPIO_REG(pin->gp_pin, DIR), reg);
		122	reg = bus_read_4(sc->gpio_mem_res, GPIO_REG(pin->gp_pin, DIR));
118	}	123	}
119		124
120	if (flags & GPIO_PIN_INVOUT) {	125	if (flags & GPIO_PIN_INVOUT) {
Lines 141-147 rt305x_gpio_pin_configure(struct rt305x_gpio_softc sc, struct gpio_pin pin, Link Here
141	pin->gp_flags \|= GPIO_PIN_REPORT;	146	pin->gp_flags \|= GPIO_PIN_REPORT;
142	GPIO_BIT_SET(sc, pin->gp_pin, RENA);	147	GPIO_BIT_SET(sc, pin->gp_pin, RENA);
143	GPIO_BIT_SET(sc, pin->gp_pin, FENA);	148	GPIO_BIT_SET(sc, pin->gp_pin, FENA);
144	device_printf(sc->dev, "Will report interrupt on pin %d\n",	149	device_printf(sc->dev, "Will report interrupt on pin %d\n",
145	pin->gp_pin);	150	pin->gp_pin);
146		151
147	}	152	}
Lines 254-260 rt305x_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) Link Here
254	if (i >= sc->gpio_npins)	259	if (i >= sc->gpio_npins)
255	return (EINVAL);	260	return (EINVAL);
256		261
257	rt305x_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);	262	rt305x_gpio_pin_configure(dev, sc, &sc->gpio_pins[i], flags);
258		263
259	return (0);	264	return (0);
260	}	265	}
Lines 275-282 rt305x_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) Link Here
275		280
276		281
277	GPIO_LOCK(sc);	282	GPIO_LOCK(sc);
278	if (value) GPIO_BIT_SET(sc, i, DATA);	283	if (value)
279	else GPIO_BIT_CLR(sc, i, DATA);	284	bus_write_4(sc->gpio_mem_res, GPIO_REG(pin, SET), GPIO_MASK(pin));
		285	else
		286	bus_write_4(sc->gpio_mem_res, GPIO_REG(pin, RESET), GPIO_MASK(pin));
280	GPIO_UNLOCK(sc);	287	GPIO_UNLOCK(sc);
281		288
282	return (0);	289	return (0);
Lines 287-292 rt305x_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) Link Here
287	{	294	{
288	struct rt305x_gpio_softc *sc = device_get_softc(dev);	295	struct rt305x_gpio_softc *sc = device_get_softc(dev);
289	int i;	296	int i;
		297	uint32_t data;
290		298
291	for (i = 0; i < sc->gpio_npins; i++) {	299	for (i = 0; i < sc->gpio_npins; i++) {
292	if (sc->gpio_pins[i].gp_pin == pin)	300	if (sc->gpio_pins[i].gp_pin == pin)
Lines 297-303 rt305x_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) Link Here
297	return (EINVAL);	305	return (EINVAL);
298		306
299	GPIO_LOCK(sc);	307	GPIO_LOCK(sc);
300	*val = GPIO_BIT_GET(sc, i, DATA);	308	data = bus_read_4(sc->gpio_mem_res, GPIO_REG(pin, DATA));
		309	data >>= GPIO_BIT_SHIFT(pin);
		310	*val = data & 1;
301	GPIO_UNLOCK(sc);	311	GPIO_UNLOCK(sc);
302		312
303	return (0);	313	return (0);
Lines 318-324 rt305x_gpio_pin_toggle(device_t dev, uint32_t pin) Link Here
318	return (EINVAL);	328	return (EINVAL);
319		329
320	GPIO_LOCK(sc);	330	GPIO_LOCK(sc);
321	GPIO_BIT_SET(sc, i, TOG);	331	bus_write_4(sc->gpio_mem_res, GPIO_REG(pin, TOG), GPIO_MASK(pin));
322	GPIO_UNLOCK(sc);	332	GPIO_UNLOCK(sc);
323		333
324	return (0);	334	return (0);
Lines 358-364 rt305x_gpio_intr(void *arg) Link Here
358	* if now reset is high, check how long	368	* if now reset is high, check how long
359	* and do reset if less than 2 seconds	369	* and do reset if less than 2 seconds
360	*/	370	*/
361	if ( reset_pin &&	371	if ( reset_pin &&
362	(time_uptime - sc->reset_gpio_ontime) < 2 )	372	(time_uptime - sc->reset_gpio_ontime) < 2 )
363	shutdown_nice(0);	373	shutdown_nice(0);
364		374
Lines 375-388 rt305x_gpio_intr(void *arg) Link Here
375	if ( (((value & input) >> i) & 1) != sc->gpio_pins[i].gp_last )	385	if ( (((value & input) >> i) & 1) != sc->gpio_pins[i].gp_last )
376	{	386	{
377	/* !system=GPIO subsystem=pin7 type=PIN_HIGH period=3 */	387	/* !system=GPIO subsystem=pin7 type=PIN_HIGH period=3 */
378	snprintf(notify , sizeof(notify ), "period=%d",	388	snprintf(notify , sizeof(notify ), "period=%d",
379	(uint32_t)time_uptime - sc->gpio_pins[i].gp_time);	389	(uint32_t)time_uptime - sc->gpio_pins[i].gp_time);
380	snprintf(pinname, sizeof(pinname), "pin%02d", i);	390	snprintf(pinname, sizeof(pinname), "pin%02d", i);
381	devctl_notify("GPIO", pinname,	391	devctl_notify("GPIO", pinname,
382	(((value & input) >> i) & 1)?"PIN_HIGH":"PIN_LOW",	392	(((value & input) >> i) & 1)?"PIN_HIGH":"PIN_LOW",
383	notify);	393	notify);
384	printf("GPIO[%s] %s %s\n", pinname,	394	printf("GPIO[%s] %s %s\n", pinname,
385	(((value & input) >> i) & 1)?"PIN_HIGH":"PIN_LOW",	395	(((value & input) >> i) & 1)?"PIN_HIGH":"PIN_LOW",
386	notify);	396	notify);
387	sc->gpio_pins[i].gp_last = ((value & input) >> i) & 1;	397	sc->gpio_pins[i].gp_last = ((value & input) >> i) & 1;
388	sc->gpio_pins[i].gp_time = time_uptime;	398	sc->gpio_pins[i].gp_time = time_uptime;
Lines 402-450 rt305x_gpio_probe(device_t dev) Link Here
402	return (0);	412	return (0);
403	}	413	}
404		414
405	static uint64_t
406	rt305x_gpio_init(device_t dev)
407	{
408	uint64_t avl = ~0ULL;
409	uint32_t gmode = rt305x_sysctl_get(SYSCTL_GPIOMODE);
410	if (!(gmode & SYSCTL_GPIOMODE_RGMII_GPIO_MODE))
411	avl &= ~RGMII_GPIO_MODE_MASK;
412	if (!(gmode & SYSCTL_GPIOMODE_SDRAM_GPIO_MODE))
413	avl &= ~SDRAM_GPIO_MODE_MASK;
414	if (!(gmode & SYSCTL_GPIOMODE_MDIO_GPIO_MODE))
415	avl &= ~MDIO_GPIO_MODE_MASK;
416	if (!(gmode & SYSCTL_GPIOMODE_JTAG_GPIO_MODE))
417	avl &= ~JTAG_GPIO_MODE_MASK;
418	if (!(gmode & SYSCTL_GPIOMODE_UARTL_GPIO_MODE))
419	avl &= ~UARTL_GPIO_MODE_MASK;
420	if (!(gmode & SYSCTL_GPIOMODE_SPI_GPIO_MODE))
421	avl &= ~SPI_GPIO_MODE_MASK;
422	if (!(gmode & SYSCTL_GPIOMODE_I2C_GPIO_MODE))
423	avl &= ~I2C_GPIO_MODE_MASK;
424	if ((gmode & SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO) !=
425	SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO)
426	avl &= ~I2C_GPIO_MODE_MASK;
427	/* D-Link DAP-1350 Board have
428	* MDIO_GPIO_MODE
429	* UARTF_GPIO_MODE
430	* SPI_GPIO_MODE
431	* I2C_GPIO_MODE
432	* So we have
433	* 00000001 10000000 01111111 11111110
434	*/
435	return (avl);
436
437	}
438
439	#define DAP1350_RESET_GPIO 10
440
441	static int	415	static int
442	rt305x_gpio_attach(device_t dev)	416	rt305x_gpio_attach(device_t dev)
443	{	417	{
444	struct rt305x_gpio_softc *sc = device_get_softc(dev);	418	struct rt305x_gpio_softc *sc = device_get_softc(dev);
445	int i;	419	int i;
446	uint64_t avlpins = 0;	420	uint32_t reg, mask, pinon, pinin;
447	sc->reset_gpio = DAP1350_RESET_GPIO;
448		421
449	KASSERT((device_get_unit(dev) == 0),	422	KASSERT((device_get_unit(dev) == 0),
450	("rt305x_gpio_gpio: Only one gpio module supported"));	423	("rt305x_gpio_gpio: Only one gpio module supported"));
Lines 462-475 rt305x_gpio_attach(device_t dev) Link Here
462	return (ENXIO);	435	return (ENXIO);
463	}	436	}
464		437
465	if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,	438	if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
466	&sc->gpio_irq_rid, RF_SHAREABLE \| RF_ACTIVE)) == NULL) {	439	&sc->gpio_irq_rid, RF_SHAREABLE \| RF_ACTIVE)) == NULL) {
467	device_printf(dev, "unable to allocate IRQ resource\n");	440	device_printf(dev, "unable to allocate IRQ resource\n");
468	rt305x_gpio_detach(dev);	441	rt305x_gpio_detach(dev);
469	return (ENXIO);	442	return (ENXIO);
470	}	443	}
471		444
472	if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,	445	if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,
473	/* rt305x_gpio_filter, */	446	/* rt305x_gpio_filter, */
474	rt305x_gpio_intr, NULL, sc, &sc->gpio_ih))) {	447	rt305x_gpio_intr, NULL, sc, &sc->gpio_ih))) {
475	device_printf(dev,	448	device_printf(dev,
Lines 479-514 rt305x_gpio_attach(device_t dev) Link Here
479	}	452	}
480		453
481	sc->dev = dev;	454	sc->dev = dev;
482	avlpins = rt305x_gpio_init(dev);	455	rt305x_gpio_pin_max(dev, &sc->gpio_npins);
483		456
484	/* Configure all pins as input */	457	/* Get the current function set */
485	/* disable interrupts for all pins */	458	reg = rt305x_sysctl_get(SYSCTL_GPIOMODE);
486	/* TODO */	459	/* Enable function bits that are required */
487		460	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
488	sc->gpio_npins = NGPIO;	461	"function_set", &mask) == 0) {
489	resource_int_value(device_get_name(dev), device_get_unit(dev),	462	device_printf(dev, "function_set: 0x%x\n", mask);
490	"pins", &sc->gpio_npins);	463	reg \|= mask;
491		464	}
		465	/* Disable function bits that are required */
		466	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
		467	"function_clear", &mask) == 0) {
		468	device_printf(dev, "function_clear: 0x%x\n", mask);
		469	reg &= ~mask;
		470	}
		471	rt305x_sysctl_set(SYSCTL_GPIOMODE, reg);
		472
		473	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
		474	"pinmask", &mask) != 0)
		475	mask = 0;
		476	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
		477	"pinon", &pinon) != 0)
		478	pinon = 0;
		479	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
		480	"pinin", &pinin) != 0)
		481	pinin = 0;
		482	device_printf(dev, "gpio pinmask=0x%x\n", mask);
		483
		484	/* Configure all pins, keep the loader settings */
		485	reg = bus_read_4(sc->gpio_mem_res, GPIO_REG(22, DIR)) << GPIO_BIT_SHIFT(22);
		486	reg \|= bus_read_4(sc->gpio_mem_res, GPIO_REG(0, DIR));
492	for (i = 0; i < sc->gpio_npins; i++) {	487	for (i = 0; i < sc->gpio_npins; i++) {
		488	if ((mask & (1 << i)) == 0)
		489	continue;
		490	snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
		491	"pin %d", i);
493	sc->gpio_pins[i].gp_pin = i;	492	sc->gpio_pins[i].gp_pin = i;
494	sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;	493	sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
495	sc->gpio_pins[i].gp_flags = 0;	494	sc->gpio_pins[i].gp_flags = (reg & (1 << i)) ? GPIO_PIN_OUTPUT : GPIO_PIN_INPUT;
		495	}
		496
		497	/* Turn on the hinted pins or configure them as inputs. */
		498	for (i = 0; i < sc->gpio_npins; i++) {
		499	if ((pinon & (1 << sc->gpio_pins[i].gp_pin)) != 0) {
		500	rt305x_gpio_pin_setflags(dev, sc->gpio_pins[i].gp_pin, GPIO_PIN_OUTPUT);
		501	rt305x_gpio_pin_set(dev, sc->gpio_pins[i].gp_pin, 1);
		502	}
		503	if ((pinin & (1 << sc->gpio_pins[i].gp_pin)) != 0)
		504	rt305x_gpio_pin_setflags(dev, sc->gpio_pins[i].gp_pin, GPIO_PIN_INPUT);
496	}	505	}
497		506
498	/* Setup reset pin interrupt */	507	/* Setup reset pin interrupt */
		508	sc->reset_gpio = -1;
499	if (TUNABLE_INT_FETCH("reset_gpio", &sc->reset_gpio)) {	509	if (TUNABLE_INT_FETCH("reset_gpio", &sc->reset_gpio)) {
500	device_printf(dev, "\tHinted reset_gpio %d\n", sc->reset_gpio);	510	device_printf(dev, "\tHinted reset_gpio %d\n", sc->reset_gpio);
501	}	511	}
502	#ifdef notyet	512	#ifdef notyet
503	if (sc->reset_gpio != -1) {	513	if (sc->reset_gpio != -1) {
504	rt305x_gpio_pin_setflags(dev, sc->reset_gpio,	514	rt305x_gpio_pin_setflags(dev, sc->reset_gpio,
505	GPIO_PIN_INPUT\|GPIO_PIN_INVOUT\|	515	GPIO_PIN_INPUT\|GPIO_PIN_INVOUT\|
506	GPIO_PIN_INVOUT\|GPIO_PIN_REPORT);	516	GPIO_PIN_INVOUT\|GPIO_PIN_REPORT);
507	device_printf(dev, "\tUse reset_gpio %d\n", sc->reset_gpio);	517	device_printf(dev, "\tUse reset_gpio %d\n", sc->reset_gpio);
508	}	518	}
509	#else	519	#else
510	if (sc->reset_gpio != -1) {	520	if (sc->reset_gpio != -1) {
511	rt305x_gpio_pin_setflags(dev, sc->reset_gpio,	521	rt305x_gpio_pin_setflags(dev, sc->reset_gpio,
512	GPIO_PIN_INPUT\|GPIO_PIN_INVOUT);	522	GPIO_PIN_INPUT\|GPIO_PIN_INVOUT);
513	device_printf(dev, "\tUse reset_gpio %d\n", sc->reset_gpio);	523	device_printf(dev, "\tUse reset_gpio %d\n", sc->reset_gpio);
514	}	524	}
Lines 622-626 static driver_t rt305x_gpio_driver = { Link Here
622	};	632	};
623	static devclass_t rt305x_gpio_devclass;	633	static devclass_t rt305x_gpio_devclass;
624		634
625	DRIVER_MODULE(rt305x_gpio, obio, rt305x_gpio_driver,	635	DRIVER_MODULE(rt305x_gpio, obio, rt305x_gpio_driver,
626	rt305x_gpio_devclass, 0, 0);	636	rt305x_gpio_devclass, 0, 0);

Lines 1-4 Link Here

(-)b/sys/mips/rt305x/rt305x_gpio.h (-11 / +62 lines)
1	/*-	1	/*-
		2	* Copyright (c) 2015, Emmanuel Vadot <manu@bidouilliste.com>
2	* Copyright (c) 2010 Aleksandr Rybalko.	3	* Copyright (c) 2010 Aleksandr Rybalko.
3	* All rights reserved.	4	* All rights reserved.
4	*	5	*
Lines 28-44 Link Here
28	#ifndef _RT305X_GPIO_H_	29	#ifndef _RT305X_GPIO_H_
29	#define _RT305X_GPIO_H_	30	#define _RT305X_GPIO_H_
30		31
31	#define NGPIO 52
32
33	#define RGMII_GPIO_MODE_MASK (0x0fffULL<<40)
34	#define SDRAM_GPIO_MODE_MASK (0xffffULL<<24)
35	#define MDIO_GPIO_MODE_MASK (0x0003ULL<<22)
36	#define JTAG_GPIO_MODE_MASK (0x001fULL<<17)	32	#define JTAG_GPIO_MODE_MASK (0x001fULL<<17)
37	#define UARTL_GPIO_MODE_MASK (0x0003ULL<<15)	33	#define UARTL_GPIO_MODE_MASK (0x0003ULL<<15)
38	#define UARTF_GPIO_MODE_MASK (0x00ffULL<<7)	34	#define UARTF_GPIO_MODE_MASK (0x00ffULL<<7)
39	#define SPI_GPIO_MODE_MASK (0x000fULL<<3)	35	#define SPI_GPIO_MODE_MASK (0x000fULL<<3)
40	#define I2C_GPIO_MODE_MASK (0x0003ULL<<1)	36	#define I2C_GPIO_MODE_MASK (0x0003ULL<<1)
41		37
		38	#if defined(RT3050F) \|\| defined(RT3052F)
		39	#define NGPIO 52
		40
		41	#define RGMII_GPIO_MODE_MASK (0x0fffULL<<40)
		42	#define SDRAM_GPIO_MODE_MASK (0xffffULL<<24)
		43	#define MDIO_GPIO_MODE_MASK (0x0003ULL<<22)
		44
42	#define GPIO23_00_INT 0x00 /* Programmed I/O Int Status */	45	#define GPIO23_00_INT 0x00 /* Programmed I/O Int Status */
43	#define GPIO23_00_EDGE 0x04 /* Programmed I/O Edge Status */	46	#define GPIO23_00_EDGE 0x04 /* Programmed I/O Edge Status */
44	#define GPIO23_00_RENA 0x08 /* Programmed I/O Int on Rising */	47	#define GPIO23_00_RENA 0x08 /* Programmed I/O Int on Rising */
Lines 78-87 Link Here
78	((g<24)?(1<<g):(g<40)?(1<<(g-24)):(1<<(g-40)))	81	((g<24)?(1<<g):(g<40)?(1<<(g-24)):(1<<(g-40)))
79	#define GPIO_BIT_SHIFT(g) ((g<24)?(g):(g<40)?(g-24):(g-40))	82	#define GPIO_BIT_SHIFT(g) ((g<24)?(g):(g<40)?(g-24):(g-40))
80		83
81	#define GPIO_READ(r, g, n) \
82	bus_read_4(r->gpio_mem_res, GPIO_REG(g, n))
83	#define GPIO_WRITE(r, g, n, v) \
84	bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), v)
85	#define GPIO_READ_ALL(r, n) \	84	#define GPIO_READ_ALL(r, n) \
86	(((uint64_t)bus_read_4(r->gpio_mem_res, GPIO23_00_##n)) \| \	85	(((uint64_t)bus_read_4(r->gpio_mem_res, GPIO23_00_##n)) \| \
87	(((uint64_t)bus_read_4(r->gpio_mem_res, GPIO39_24_##n)) << 24) \|\	86	(((uint64_t)bus_read_4(r->gpio_mem_res, GPIO39_24_##n)) << 24) \|\
Lines 91-96 Link Here
91	bus_write_4(r->gpio_mem_res, GPIO39_24_##n, (v>>24)&0x0000ffff);\	90	bus_write_4(r->gpio_mem_res, GPIO39_24_##n, (v>>24)&0x0000ffff);\
92	bus_write_4(r->gpio_mem_res, GPIO51_40_##n, (v>>40)&0x00000fff);}	91	bus_write_4(r->gpio_mem_res, GPIO51_40_##n, (v>>40)&0x00000fff);}
93		92
		93	#endif
		94
		95	#ifdef RT5350F
		96	#define NGPIO 28
		97
		98	#define SPI_CS1_GPIO_MODE_MASK (0x0001ULL<<27)
		99	#define PHY_LED_GPIO_MODE_MASK (0x0003ULL<<22)
		100
		101	#define GPIO21_00_INT 0x00 /* Programmed I/O Int Status */
		102	#define GPIO21_00_EDGE 0x04 /* Programmed I/O Edge Status */
		103	#define GPIO21_00_RENA 0x08 /* Programmed I/O Int on Rising */
		104	#define GPIO21_00_FENA 0x0C /* Programmed I/O Int on Falling */
		105	#define GPIO21_00_DATA 0x20 /* Programmed I/O Data */
		106	#define GPIO21_00_DIR 0x24 /* Programmed I/O Direction */
		107	#define GPIO21_00_POL 0x28 /* Programmed I/O Pin Polarity */
		108	#define GPIO21_00_SET 0x2C /* Set PIO Data Bit */
		109	#define GPIO21_00_RESET 0x30 /* Clear PIO Data bit */
		110	#define GPIO21_00_TOG 0x34 /* Toggle PIO Data bit */
		111
		112	#define GPIO27_22_INT 0x60
		113	#define GPIO27_22_EDGE 0x64
		114	#define GPIO27_22_RENA 0x68
		115	#define GPIO27_22_FENA 0x6C
		116	#define GPIO27_22_DATA 0x70
		117	#define GPIO27_22_DIR 0x74
		118	#define GPIO27_22_POL 0x78
		119	#define GPIO27_22_SET 0x7C
		120	#define GPIO27_22_RESET 0x80
		121	#define GPIO27_22_TOG 0x84
		122
		123	#define GPIO_REG(g, n) \
		124	((g < 22) ? (GPIO21_00_##n) : (GPIO27_22_##n))
		125
		126	#define GPIO_MASK(g) \
		127	((g < 22) ? (1UL << g ) : (1UL << (g - 22)))
		128
		129	#define GPIO_BIT_SHIFT(g) (g < 22) ? (g) : (g - 22)
		130
		131	#define GPIO_READ_ALL(r, n) \
		132	(((uint64_t)bus_read_4(r->gpio_mem_res, GPIO21_00_##n)) \| \
		133	(((uint64_t)bus_read_4(r->gpio_mem_res, GPIO27_22_##n)) << 22))
		134	#define GPIO_WRITE_ALL(r, n, v) \
		135	{bus_write_4(r->gpio_mem_res,GPIO21_00_##n, v &0x00ffffff);\
		136	bus_write_4(r->gpio_mem_res, GPIO27_22_##n, (v>>22)&0x0000ffff);}
		137
		138	#endif
		139
		140
		141	#define GPIO_READ(r, g, n) \
		142	bus_read_4(r->gpio_mem_res, GPIO_REG(g, n))
		143	#define GPIO_WRITE(r, g, n, v) \
		144	bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), v)
94		145
95	#define GPIO_BIT_CLR(r, g, n) \	146	#define GPIO_BIT_CLR(r, g, n) \
96	bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), \	147	bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), \
Lines 100-107 Link Here
100	bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) \| GPIO_MASK(g))	151	bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) \| GPIO_MASK(g))
101		152
102	#define GPIO_BIT_GET(r, g, n) \	153	#define GPIO_BIT_GET(r, g, n) \
103	((bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) >> \	154	((bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) >> \
104	GPIO_BIT_SHIFT(g)) & 1)	155	GPIO_BIT_SHIFT(g)) & 1)
105		156
106	#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->gpio_mtx)	157	#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->gpio_mtx)
107	#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->gpio_mtx)	158	#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->gpio_mtx)

Lines 1-4 Link Here

(-)b/sys/mips/rt305x/rt305xreg.h (-50 / +75 lines)
1	/*-	1	/*-
		2	* Copyright (c) 2015, Emmanuel Vadot <manu@bidouilliste.com>
2	* Copyright (c) 2010 Aleksandr Rybalko.	3	* Copyright (c) 2010 Aleksandr Rybalko.
3	* All rights reserved.	4	* All rights reserved.
4	*	5	*
Lines 29-47 Link Here
29	#ifndef _RT305XREG_H_	30	#ifndef _RT305XREG_H_
30	#define _RT305XREG_H_	31	#define _RT305XREG_H_
31		32
32	/* XXX: must move to config */
33	#define RT305X 1
34	#define RT305XF 1
35	#define RT3052F 1
36	#define __U_BOOT__ 1
37	/* XXX: must move to config */
38
39	#ifdef RT3052F	33	#ifdef RT3052F
40	#define PLATFORM_COUNTER_FREQ (384 * 1000 * 1000)	34	#define PLATFORM_COUNTER_FREQ (384 * 1000 * 1000)
41	#endif	35	#endif
42	#ifdef RT3050F	36	#ifdef RT3050F
43	#define PLATFORM_COUNTER_FREQ (320 * 1000 * 1000)	37	#define PLATFORM_COUNTER_FREQ (320 * 1000 * 1000)
44	#endif	38	#endif
		39	#ifdef RT5350F
		40	#define PLATFORM_COUNTER_FREQ (360 * 1000 * 1000)
		41	#endif
45	#ifndef PLATFORM_COUNTER_FREQ	42	#ifndef PLATFORM_COUNTER_FREQ
46	#error "Nor RT3052F nor RT3050F defined"	43	#error "Nor RT3052F nor RT3050F defined"
47	#endif	44	#endif
Lines 60-75 Link Here
60	#define INTCTL_END 0x100002FF	57	#define INTCTL_END 0x100002FF
61	#define MEMCTRL_BASE 0x10000300	58	#define MEMCTRL_BASE 0x10000300
62	#define MEMCTRL_END 0x100003FF /* SDRAM & Flash/SRAM */	59	#define MEMCTRL_END 0x100003FF /* SDRAM & Flash/SRAM */
		60	#if defined(RT3050F) \|\| defined(RT3052F)
63	#define PCM_BASE 0x10000400	61	#define PCM_BASE 0x10000400
64	#define PCM_END 0x100004FF	62	#define PCM_END 0x100004FF
		63	#endif
65	#define UART_BASE 0x10000500	64	#define UART_BASE 0x10000500
66	#define UART_END 0x100005FF	65	#define UART_END 0x100005FF
67	#define PIO_BASE 0x10000600	66	#define PIO_BASE 0x10000600
68	#define PIO_END 0x100006FF	67	#define PIO_END 0x100006FF
		68	#if defined(RT3050F) \|\| defined(RT3052F)
69	#define GDMA_BASE 0x10000700	69	#define GDMA_BASE 0x10000700
70	#define GDMA_END 0x100007FF /* Generic DMA */	70	#define GDMA_END 0x100007FF /* Generic DMA */
71	#define NANDFC_BASE 0x10000800	71	#define NANDFC_BASE 0x10000800
72	#define NANDFC_END 0x100008FF /* NAND Flash Controller */	72	#define NANDFC_END 0x100008FF /* NAND Flash Controller */
		73	#endif
73	#define I2C_BASE 0x10000900	74	#define I2C_BASE 0x10000900
74	#define I2C_END 0x100009FF	75	#define I2C_END 0x100009FF
75	#define I2S_BASE 0x10000A00	76	#define I2S_BASE 0x10000A00
Lines 85-109 Link Here
85	#define ETHSW_END 0x10117FFF /* Ethernet Switch */	86	#define ETHSW_END 0x10117FFF /* Ethernet Switch */
86	#define ROM_BASE 0x10118000	87	#define ROM_BASE 0x10118000
87	#define ROM_END 0x10119FFF	88	#define ROM_END 0x10119FFF
		89	#ifdef RT5350F
		90	#define USB_OTG_BASE 0x10120000
		91	#define USB_OTG_END 0x1012FFFF
		92	#endif
88	#define WLAN_BASE 0x10180000	93	#define WLAN_BASE 0x10180000
89	#define WLAN_END 0x101BFFFF /* 802.11n MAC/BBP */	94	#define WLAN_END 0x101BFFFF /* 802.11n MAC/BBP */
		95	#if defined(RT3050F) \|\| defined(RT3052F)
90	#define USB_OTG_BASE 0x101C0000	96	#define USB_OTG_BASE 0x101C0000
91	#define USB_OTG_END 0x101FFFFF	97	#define USB_OTG_END 0x101FFFFF
		98	#endif
92	#define EMEM_BASE 0x1B000000	99	#define EMEM_BASE 0x1B000000
93	#define EMEM_END 0x1BFFFFFF /* External SRAM/Flash */	100	#define EMEM_END 0x1BFFFFFF /* External SRAM/Flash */
		101	#ifdef RT5350F
		102	#define BOOT_ROM_BASE 0x1C000000
		103	#define BOOT_ROM_END 0x1C003FFF
		104	#endif
		105	#if defined(RT3050F) \|\| defined(RT3052F)
94	#define FLASH_BASE 0x1F000000	106	#define FLASH_BASE 0x1F000000
95	#define FLASH_END 0x1FFFFFFF /* Flash window */	107	#define FLASH_END 0x1FFFFFFF /* Flash window */
		108	#endif
96		109
97	#define OBIO_MEM_BASE SYSCTL_BASE	110	#define OBIO_MEM_BASE SYSCTL_BASE
98	#define OBIO_MEM_START OBIO_MEM_BASE	111	#define OBIO_MEM_START OBIO_MEM_BASE
		112	#if defined(RT3050F) \|\| defined(RT2052F)
99	#define OBIO_MEM_END FLASH_END	113	#define OBIO_MEM_END FLASH_END
100		114	#endif
101		115	#ifdef RT5350F
		116	#define OBIO_MEM_END BOOT_ROM_END
		117	#endif
102		118
103	/* System Control */	119	/* System Control */
104	#define SYSCTL_CHIPID0_3 0x00 /* 'R''T''3''0' */	120	#define SYSCTL_CHIPID0_3 0x00 /* 'R''T''3''0' for RT305X or 'R' 'T' '5' '3' for RT5350 */
105	#define SYSCTL_CHIPID4_7 0x04 /* '5''2'' '' ' */	121	#define SYSCTL_CHIPID4_7 0x04 /* '5''2'' '' ' for RT305X or '5' '0' ' ' ' ' for RT5350 */
		122	#ifdef RT5350F
		123	#define SYSCTL_REVID 0x0C /* 0x1 0x1 - */
		124	#endif
		125
106	#define SYSCTL_SYSCFG 0x10	126	#define SYSCTL_SYSCFG 0x10
		127	#if defined(RT3050F) \|\| defined(RT3052F)
107	#define SYSCTL_SYSCFG_INIC_EE_SDRAM (1<<29)	128	#define SYSCTL_SYSCFG_INIC_EE_SDRAM (1<<29)
108	#define SYSCTL_SYSCFG_INIC_8MB_SDRAM (1<<28)	129	#define SYSCTL_SYSCFG_INIC_8MB_SDRAM (1<<28)
109	#define SYSCTL_SYSCFG_GE0_MODE_MASK 0x03000000	130	#define SYSCTL_SYSCFG_GE0_MODE_MASK 0x03000000
Lines 129-134 Link Here
129	#define SYSCTL_SYSCFG_SRAM_CS_MODE_WDOG_RST 1	150	#define SYSCTL_SYSCFG_SRAM_CS_MODE_WDOG_RST 1
130	#define SYSCTL_SYSCFG_SRAM_CS_MODE_BT_COEX 2	151	#define SYSCTL_SYSCFG_SRAM_CS_MODE_BT_COEX 2
131	#define SYSCTL_SYSCFG_SDRAM_CLK_DRV (1<<0) /* 8mA/12mA */	152	#define SYSCTL_SYSCFG_SDRAM_CLK_DRV (1<<0) /* 8mA/12mA */
		153	#endif
		154	#ifdef RT5350F
		155	#define SYSCTL_SYSCFG_PULL_EN (1<<26)
		156	#define SYSCTL_SYSCFG_SDR_PAD_DRV_MASK 0x0700000
		157	#define SYSCTL_SYSCFG_SDR_PAD_DRV_SHIFT 20
		158	#define SYSCTL_SYSCFG_SDR_PAD_DRV_0 0
		159	#define SYSCTL_SYSCFG_SDR_PAD_DRV_1 1
		160	#define SYSCTL_SYSCFG_SDR_PAD_DRV_2 2
		161	#define SYSCTL_SYSCFG_USB0_MODE (1<<10) /* 0 device / 1 host */
		162	#define SYSCTL_SYSCFG_USB_PHY_EN (1<<9)
		163	#endif
132		164
133	#define SYSCTL_TESTSTAT 0x18	165	#define SYSCTL_TESTSTAT 0x18
134	#define SYSCTL_TESTSTAT2 0x1C	166	#define SYSCTL_TESTSTAT2 0x1C
Lines 142-147 Link Here
142	#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_3NS_DELAY 3	174	#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_3NS_DELAY 3
143		175
144	#define SYSCTL_CLKCFG1 0x30	176	#define SYSCTL_CLKCFG1 0x30
		177	#if defined(RT3050F) \|\| defined(RT3052F)
145	#define SYSCTL_CLKCFG1_PBUS_DIV_CLK_BY2 (1<<30)	178	#define SYSCTL_CLKCFG1_PBUS_DIV_CLK_BY2 (1<<30)
146	#define SYSCTL_CLKCFG1_OTG_CLK_EN (1<<18)	179	#define SYSCTL_CLKCFG1_OTG_CLK_EN (1<<18)
147	#define SYSCTL_CLKCFG1_I2S_CLK_EN (1<<15)	180	#define SYSCTL_CLKCFG1_I2S_CLK_EN (1<<15)
Lines 152-157 Link Here
152	#define SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT (1<<6)	185	#define SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT (1<<6)
153	#define SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK 0x0000003f	186	#define SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK 0x0000003f
154	#define SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT 0	187	#define SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT 0
		188	#endif
		189	#ifdef RT5350F
		190	#define SYSCTL_CLKCFG1_SYSTICK_EN (1<<29)
		191	#define SYSCTL_CLKCFG1_PDMA_CSR_CLK_GATE_BYP (1<<23)
		192	#define SYSCTL_CLKCFG1_UPHY0_CLK_EN (1<<18)
		193	#endif
155		194
156	#define SYSCTL_RSTCTRL 0x34	195	#define SYSCTL_RSTCTRL 0x34
157	#define SYSCTL_RSTCTRL_ETHSW (1<<23)	196	#define SYSCTL_RSTCTRL_ETHSW (1<<23)
Lines 176-185 Link Here
176	#define SYSCTL_RSTSTAT_SWSYSRST (1<<2)	215	#define SYSCTL_RSTSTAT_SWSYSRST (1<<2)
177	#define SYSCTL_RSTSTAT_WDRST (1<<1)	216	#define SYSCTL_RSTSTAT_WDRST (1<<1)
178		217
		218	#ifdef RT5350F
		219	#define SYSCTL_CPU_SYS_CLKCFG 0x3C
		220
		221	#define SYSCTL_CLK_LUT_CFG 0x40
		222
		223	#define SYSCTL_CPU_CLK_AUTO_CFG 0x44
		224
		225	#define SYSCTL_CPU_PLL_DYN_CFG 0x48
		226
		227	#define SYSCTL_RF_RX_SD_CFG 0x58
		228
		229	#endif
		230
179	#define SYSCTL_GPIOMODE 0x60	231	#define SYSCTL_GPIOMODE 0x60
		232	#if defined(RT3050F) \|\| defined(RT3052F)
180	#define SYSCTL_GPIOMODE_RGMII_GPIO_MODE (1<<9)	233	#define SYSCTL_GPIOMODE_RGMII_GPIO_MODE (1<<9)
181	#define SYSCTL_GPIOMODE_SDRAM_GPIO_MODE (1<<8)	234	#define SYSCTL_GPIOMODE_SDRAM_GPIO_MODE (1<<8)
182	#define SYSCTL_GPIOMODE_MDIO_GPIO_MODE (1<<7)	235	#define SYSCTL_GPIOMODE_MDIO_GPIO_MODE (1<<7)
		236	#endif
183	#define SYSCTL_GPIOMODE_JTAG_GPIO_MODE (1<<6)	237	#define SYSCTL_GPIOMODE_JTAG_GPIO_MODE (1<<6)
184	#define SYSCTL_GPIOMODE_UARTL_GPIO_MODE (1<<5)	238	#define SYSCTL_GPIOMODE_UARTL_GPIO_MODE (1<<5)
185	#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_UARTF (0<<2)	239	#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_UARTF (0<<2)
Lines 193-200 Link Here
193	#define SYSCTL_GPIOMODE_SPI_GPIO_MODE (1<<1)	247	#define SYSCTL_GPIOMODE_SPI_GPIO_MODE (1<<1)
194	#define SYSCTL_GPIOMODE_I2C_GPIO_MODE (1<<0)	248	#define SYSCTL_GPIOMODE_I2C_GPIO_MODE (1<<0)
195		249
		250	#if defined(RT3050F) \|\| defined(RT3052F)
196	#define SYSCTL_MEMO0 0x68	251	#define SYSCTL_MEMO0 0x68
197	#define SYSCTL_MEMO1 0x6C	252	#define SYSCTL_MEMO1 0x6C
		253	#endif
		254
198		255
199	/* Timer */	256	/* Timer */
200	#define TIMER_TMRSTAT 0x00	257	#define TIMER_TMRSTAT 0x00
Lines 247-258 Link Here
247	#define IC_INT_ENA 0x34	304	#define IC_INT_ENA 0x34
248	#define IC_INT_DIS 0x38	305	#define IC_INT_DIS 0x38
249		306
		307	#define IC_UDEV 19
250	#define IC_OTG 18	308	#define IC_OTG 18
251	#define IC_ETHSW 17	309	#define IC_ETHSW 17
252	#define IC_UARTLITE 12	310	#define IC_UARTLITE 12
253	#define IC_I2S 10	311	#define IC_I2S 10
254	#define IC_PERFC 9	312	#define IC_PERFC 9
		313	#if defined(RT3050F) \|\| defined(RT2052)
255	#define IC_NAND 8	314	#define IC_NAND 8
		315	#endif
256	#define IC_DMA 7	316	#define IC_DMA 7
257	#define IC_PIO 6	317	#define IC_PIO 6
258	#define IC_UART 5	318	#define IC_UART 5
Lines 263-268 Link Here
263	#define IC_SYSCTL 0	323	#define IC_SYSCTL 0
264		324
265	#define IC_LINE_GLOBAL (1<<31) /* Only for DIS/ENA regs */	325	#define IC_LINE_GLOBAL (1<<31) /* Only for DIS/ENA regs */
		326	#ifdef RT5350F
		327	#define IC_LINE_UDEV (1<<19)
		328	#endif
266	#define IC_LINE_OTG (1<<18)	329	#define IC_LINE_OTG (1<<18)
267	#define IC_LINE_ETHSW (1<<17)	330	#define IC_LINE_ETHSW (1<<17)
268	#define IC_LINE_UARTLITE (1<<12)	331	#define IC_LINE_UARTLITE (1<<12)
Lines 278-322 Link Here
278	#define IC_LINE_TIMER0 (1<<1)	341	#define IC_LINE_TIMER0 (1<<1)
279	#define IC_LINE_SYSCTL (1<<0)	342	#define IC_LINE_SYSCTL (1<<0)
280		343
281	#define IC_INT_MASK 0x000617ff	344	#define IC_INT_MASK 0x000717ff
282
283	/* GPIO */
284
285	#define GPIO23_00_INT 0x00 /* Programmed I/O Int Status */
286	#define GPIO23_00_EDGE 0x04 /* Programmed I/O Edge Status */
287	#define GPIO23_00_RENA 0x08 /* Programmed I/O Int on Rising */
288	#define GPIO23_00_FENA 0x0C /* Programmed I/O Int on Falling */
289	#define GPIO23_00_DATA 0x20 /* Programmed I/O Data */
290	#define GPIO23_00_DIR 0x24 /* Programmed I/O Direction */
291	#define GPIO23_00_POL 0x28 /* Programmed I/O Pin Polarity */
292	#define GPIO23_00_SET 0x2C /* Set PIO Data Bit */
293	#define GPIO23_00_RESET 0x30 /* Clear PIO Data bit */
294	#define GPIO23_00_TOG 0x34 /* Toggle PIO Data bit */
295
296	#define GPIO39_24_INT 0x38
297	#define GPIO39_24_EDGE 0x3c
298	#define GPIO39_24_RENA 0x40
299	#define GPIO39_24_FENA 0x44
300	#define GPIO39_24_DATA 0x48
301	#define GPIO39_24_DIR 0x4c
302	#define GPIO39_24_POL 0x50
303	#define GPIO39_24_SET 0x54
304	#define GPIO39_24_RESET 0x58
305	#define GPIO39_24_TOG 0x5c
306
307	#define GPIO51_40_INT 0x60
308	#define GPIO51_40_EDGE 0x64
309	#define GPIO51_40_RENA 0x68
310	#define GPIO51_40_FENA 0x6C
311	#define GPIO51_40_DATA 0x70
312	#define GPIO51_40_DIR 0x74
313	#define GPIO51_40_POL 0x78
314	#define GPIO51_40_SET 0x7C
315	#define GPIO51_40_RESET 0x80
316	#define GPIO51_40_TOG 0x84
317
318
319
320		345
321	#define GDMA_CHANNEL_REQ0 0	346	#define GDMA_CHANNEL_REQ0 0
322	#define GDMA_CHANNEL_REQ1 1 /* (NAND-flash) */	347	#define GDMA_CHANNEL_REQ1 1 /* (NAND-flash) */