Attachment #199074 for bug #222079

Lines 74-79 __FBSDID("$FreeBSD: stable/11/sys/dev/ic Link Here

(-)ichwd.c (-3 / +52 lines)
74		74
75	#include <dev/ichwd/ichwd.h>	75	#include <dev/ichwd/ichwd.h>
76		76
		77	#include <x86/pci_cfgreg.h>
		78	#include <dev/pci/pcivar.h>
		79	#include <dev/pci/pci_private.h>
		80
77	static struct ichwd_device ichwd_devices[] = {	81	static struct ichwd_device ichwd_devices[] = {
78	{ DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1, 1 },	82	{ DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1, 1 },
79	{ DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1, 1 },	83	{ DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1, 1 },
Lines 289-294 static struct ichwd_device ichwd_devices Link Here
289		293
290	static struct ichwd_device ichwd_smb_devices[] = {	294	static struct ichwd_device ichwd_smb_devices[] = {
291	{ DEVICEID_LEWISBURG_SMB, "Lewisburg watchdog timer", 10, 4 },	295	{ DEVICEID_LEWISBURG_SMB, "Lewisburg watchdog timer", 10, 4 },
		296	{ DEVICEID_SRPT_LP_SMB, "Sunrise Point-LP watchdog timer", 10, 4 },
292	{ 0, NULL, 0, 0 },	297	{ 0, NULL, 0, 0 },
293	};	298	};
294		299
Lines 307-312 static devclass_t ichwd_devclass; Link Here
307	/* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */	312	/* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */
308	#define ichwd_read_pmc_4(sc, off) \	313	#define ichwd_read_pmc_4(sc, off) \
309	bus_read_4((sc)->gcs_res, (off))	314	bus_read_4((sc)->gcs_res, (off))
		315	#define ichwd_read_p2sb_4(sc, off) \
		316	bus_read_4((sc)->p2sb_res, (off))
310		317
311	#define ichwd_write_tco_1(sc, off, val) \	318	#define ichwd_write_tco_1(sc, off, val) \
312	bus_write_1((sc)->tco_res, (off), (val))	319	bus_write_1((sc)->tco_res, (off), (val))
Lines 321-326 static devclass_t ichwd_devclass; Link Here
321	/* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */	328	/* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */
322	#define ichwd_write_pmc_4(sc, off, val) \	329	#define ichwd_write_pmc_4(sc, off, val) \
323	bus_write_4((sc)->gcs_res, (off), (val))	330	bus_write_4((sc)->gcs_res, (off), (val))
		331	#define ichwd_write_p2sb_4(sc, off, val) \
		332	bus_write_4((sc)->p2sb_res, (off), (val))
324		333
325	#define ichwd_verbose_printf(dev, ...) \	334	#define ichwd_verbose_printf(dev, ...) \
326	do { \	335	do { \
Lines 493-501 ichwd_clear_noreboot(struct ichwd_softc Link Here
493	rc = EIO;	502	rc = EIO;
494	break;	503	break;
495	case 4:	504	case 4:
496	/*	505	status = ichwd_read_p2sb_4(sc, 0xc6000c);
497	* TODO. This needs access to a hidden PCI device at 31:1.	506	status &= ~ICH_GEN_STA_NO_REBOOT;
498	*/	507	ichwd_write_p2sb_4(sc, 0xc6000c, status);
		508	status = ichwd_read_p2sb_4(sc, 0xc6000c);
		509	if (status & ICH_GEN_STA_NO_REBOOT)
		510	rc = EIO;
499	break;	511	break;
500	default:	512	default:
501	ichwd_verbose_printf(sc->device,	513	ichwd_verbose_printf(sc->device,
Lines 704-709 ichwd_smb_attach(device_t dev) Link Here
704	device_t smb;	716	device_t smb;
705	uint32_t acpi_base;	717	uint32_t acpi_base;
706		718
		719	uint32_t cfg[2];
		720	uint64_t p2sb;
		721
707	sc = device_get_softc(dev);	722	sc = device_get_softc(dev);
708	smb = ichwd_find_smb_dev(device_get_parent(dev), &id_p);	723	smb = ichwd_find_smb_dev(device_get_parent(dev), &id_p);
709	if (smb == NULL)	724	if (smb == NULL)
Lines 744-749 ichwd_smb_attach(device_t dev) Link Here
744	return (ENXIO);	759	return (ENXIO);
745	}	760	}
746		761
		762	/* Unhide and enumerate p2sb device. */
		763	pci_cfgregwrite(0, 31, 1, 0xe1, 0, 1);
		764	if ((sc->p2sb = pci_find_dbsf(0, 0, 31, 1)) == NULL) {
		765	device_t bus = device_get_parent(smb);
		766	struct pci_devinfo *dinfo = pci_read_device(
		767	device_get_parent(bus), bus, 0, 0, 31, 1);
		768	pci_add_child(bus, dinfo);
		769	if ((sc->p2sb = pci_find_dbsf(0, 0, 31, 1)) == NULL)
		770	return (ENXIO);
		771	}
		772	/* Get the 64 bit base address and hide the device again. */
		773	cfg[0] = pci_cfgregread(0, 31, 1, 0x10, 4);
		774	cfg[1] = pci_cfgregread(0, 31, 1, 0x10 + 4, 4);
		775	pci_cfgregwrite(0, 31, 1, 0xe1, 1, 1);
		776	p2sb = cfg[0] & 0xfffffff0;
		777	p2sb \|= ((uint64_t) cfg[1] << 32);
		778
		779	/* Map the address. */
		780	sc->p2sb_rid = 0x10;
		781	sc->p2sb_res = bus_alloc_resource(
		782	sc->p2sb, SYS_RES_MEMORY, &sc->p2sb_rid,
		783	p2sb, p2sb + 0xfffffe, 0xffffff,
		784	RF_ACTIVE\|RF_SHAREABLE);
		785	if (sc->p2sb_res == NULL) {
		786	device_printf(dev, "unable to reserve hidden P2SB registers\n");
		787	return (ENXIO);
		788	}
		789
747	return (0);	790	return (0);
748	}	791	}
749		792
Lines 852-857 ichwd_attach(device_t dev) Link Here
852	if (sc->gcs_res != NULL)	895	if (sc->gcs_res != NULL)
853	bus_release_resource(sc->ich, SYS_RES_MEMORY,	896	bus_release_resource(sc->ich, SYS_RES_MEMORY,
854	sc->gcs_rid, sc->gcs_res);	897	sc->gcs_rid, sc->gcs_res);
		898	if (sc->p2sb_res != NULL)
		899	bus_release_resource(sc->p2sb, SYS_RES_MEMORY,
		900	sc->p2sb_rid, sc->p2sb_res);
855		901
856	return (ENXIO);	902	return (ENXIO);
857	}	903	}
Lines 887-892 ichwd_detach(device_t dev) Link Here
887	if (sc->gcs_res)	933	if (sc->gcs_res)
888	bus_release_resource(sc->ich, SYS_RES_MEMORY, sc->gcs_rid,	934	bus_release_resource(sc->ich, SYS_RES_MEMORY, sc->gcs_rid,
889	sc->gcs_res);	935	sc->gcs_res);
		936	if (sc->p2sb_res)
		937	bus_release_resource(sc->p2sb, SYS_RES_MEMORY, sc->p2sb_rid,
		938	sc->p2sb_res);
890		939
891	return (0);	940	return (0);
892	}	941	}

Lines 57-62 struct ichwd_softc { Link Here

(-)ichwd.h (+5 lines)
57	int gcs_rid;	57	int gcs_rid;
58	struct resource *gcs_res;	58	struct resource *gcs_res;
59		59
		60	device_t p2sb;
		61	int p2sb_rid;
		62	struct resource *p2sb_res;
		63
60	eventhandler_tag ev_tag;	64	eventhandler_tag ev_tag;
61	};	65	};
62		66
Lines 271-276 struct ichwd_softc { Link Here
271	#define DEVICEID_WCPT_LP7 0x9cc7	275	#define DEVICEID_WCPT_LP7 0x9cc7
272	#define DEVICEID_WCPT_LP9 0x9cc9	276	#define DEVICEID_WCPT_LP9 0x9cc9
273	#define DEVICEID_LEWISBURG_SMB 0xa1a3	277	#define DEVICEID_LEWISBURG_SMB 0xa1a3
		278	#define DEVICEID_SRPT_LP_SMB 0x9d23
274		279
275	/* ICH LPC Interface Bridge Registers (ICH5 and older) */	280	/* ICH LPC Interface Bridge Registers (ICH5 and older) */
276	#define ICH_GEN_STA 0xd4	281	#define ICH_GEN_STA 0xd4

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