Added
Link Here
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From b8f4b69aaaade0e3872597f1597506824f25434d Mon Sep 17 00:00:00 2001 |
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From: Alex Coplan <alex.coplan@arm.com> |
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Date: Wed, 19 May 2021 10:38:23 +0100 |
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Subject: [PATCH 122/169] arm: Fix bugs with MVE vmov from two GPRs to vector |
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lanes |
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|
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The initial problem I wanted to fix here is that GAS was rejecting MVE |
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instructions such as: |
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|
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vmov q3[2], q3[0], r2, r2 |
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|
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with: |
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|
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Error: General purpose registers may not be the same -- `vmov q3[2],q3[0],r2,r2' |
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|
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which is incorrect; such instructions are valid. Note that for moves in |
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the other direction, e.g.: |
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|
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vmov r2, r2, q3[2], q3[0] |
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|
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GAS is correct in rejecting this as it does not make sense to move both |
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lanes into the same register (the Arm ARM says this is CONSTRAINED |
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UNPREDICTABLE). |
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|
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After fixing this issue, I added assembly/disassembly tests for these |
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vmovs. This revealed several disassembly issues, including incorrectly |
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marking the moves into vector lanes as UNPREDICTABLE, and disassembling |
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many of the vmovs as vector loads. These are now fixed. |
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|
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Regtested on arm-eabi, no regressions. |
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|
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OK for trunk? What about backports? |
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|
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Thanks, |
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Alex |
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|
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gas/ChangeLog: |
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|
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* config/tc-arm.c (do_mve_mov): Only reject vmov if we're moving |
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into the same GPR twice. |
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* testsuite/gas/arm/mve-vmov-bad-2.l: Tweak error message. |
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* testsuite/gas/arm/mve-vmov-3.d: New test. |
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* testsuite/gas/arm/mve-vmov-3.s: New test. |
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|
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opcodes/ChangeLog: |
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|
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* arm-dis.c (mve_opcodes): Fix disassembly of |
48 |
MVE_VMOV2_GP_TO_VEC_LANE when idx == 1. |
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(is_mve_encoding_conflict): MVE vector loads should not match |
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when P = W = 0. |
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(is_mve_unpredictable): It's not unpredictable to use the same |
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source register twice (for MVE_VMOV2_GP_TO_VEC_LANE). |
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--- |
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gas/ChangeLog | 8 ++ |
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gas/config/tc-arm.c | 4 +- |
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gas/testsuite/gas/arm/mve-vmov-3.d | 169 +++++++++++++++++++++++++ |
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gas/testsuite/gas/arm/mve-vmov-3.s | 160 +++++++++++++++++++++++ |
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gas/testsuite/gas/arm/mve-vmov-bad-2.l | 2 +- |
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opcodes/ChangeLog | 9 ++ |
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opcodes/arm-dis.c | 7 +- |
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7 files changed, 354 insertions(+), 5 deletions(-) |
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create mode 100644 gas/testsuite/gas/arm/mve-vmov-3.d |
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create mode 100644 gas/testsuite/gas/arm/mve-vmov-3.s |
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|
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diff --git gas/ChangeLog gas/ChangeLog |
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index bd87aca2525..e747d7dd8a9 100644 |
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--- gas/ChangeLog |
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+++ gas/ChangeLog |
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@@ -1,3 +1,11 @@ |
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+2021-05-19 Alex Coplan <alex.coplan@arm.com> |
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+ |
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+ * config/tc-arm.c (do_mve_mov): Only reject vmov if we're moving |
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+ into the same GPR twice. |
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+ * testsuite/gas/arm/mve-vmov-bad-2.l: Tweak error message. |
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+ * testsuite/gas/arm/mve-vmov-3.d: New test. |
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+ * testsuite/gas/arm/mve-vmov-3.s: New test. |
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+ |
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2021-04-23 Eric Botcazou<ebotcazou@adacore.com> |
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|
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* testsuite/gas/elf/section25.d: Run it everywhere. |
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diff --git gas/config/tc-arm.c gas/config/tc-arm.c |
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index ff962daf749..d59e14930c3 100644 |
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--- gas/config/tc-arm.c |
84 |
+++ gas/config/tc-arm.c |
85 |
@@ -20013,8 +20013,8 @@ do_mve_mov (int toQ) |
86 |
constraint (inst.operands[Q0].reg != inst.operands[Q1].reg + 2, |
87 |
_("Index one must be [2,3] and index two must be two less than" |
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" index one.")); |
89 |
- constraint (inst.operands[Rt].reg == inst.operands[Rt2].reg, |
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- _("General purpose registers may not be the same")); |
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+ constraint (!toQ && inst.operands[Rt].reg == inst.operands[Rt2].reg, |
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+ _("Destination registers may not be the same")); |
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constraint (inst.operands[Rt].reg == REG_SP |
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|| inst.operands[Rt2].reg == REG_SP, |
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BAD_SP); |
96 |
diff --git gas/testsuite/gas/arm/mve-vmov-3.d gas/testsuite/gas/arm/mve-vmov-3.d |
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new file mode 100644 |
98 |
index 00000000000..5355b4ac4cb |
99 |
--- /dev/null |
100 |
+++ gas/testsuite/gas/arm/mve-vmov-3.d |
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@@ -0,0 +1,169 @@ |
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+# name: MVE vmov (between two 32-bit vector lanes and two GPRs) |
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+# as: -march=armv8.1-m.main+mve |
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+# objdump: -dr -marmv8.1-m.main |
105 |
+ |
106 |
+.*: +file format .*arm.* |
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+ |
108 |
+Disassembly of section .text: |
109 |
+ |
110 |
+0+ <.*>: |
111 |
+.*: ec01 2f00 vmov r0, r1, q1\[2\], q1\[0\] |
112 |
+.*: ec01 4f00 vmov r0, r1, q2\[2\], q2\[0\] |
113 |
+.*: ec01 6f00 vmov r0, r1, q3\[2\], q3\[0\] |
114 |
+.*: ec01 8f00 vmov r0, r1, q4\[2\], q4\[0\] |
115 |
+.*: ec01 af00 vmov r0, r1, q5\[2\], q5\[0\] |
116 |
+.*: ec01 cf00 vmov r0, r1, q6\[2\], q6\[0\] |
117 |
+.*: ec01 ef00 vmov r0, r1, q7\[2\], q7\[0\] |
118 |
+.*: ec00 0f01 vmov r1, r0, q0\[2\], q0\[0\] |
119 |
+.*: ec00 0f02 vmov r2, r0, q0\[2\], q0\[0\] |
120 |
+.*: ec00 0f03 vmov r3, r0, q0\[2\], q0\[0\] |
121 |
+.*: ec00 0f04 vmov r4, r0, q0\[2\], q0\[0\] |
122 |
+.*: ec00 0f05 vmov r5, r0, q0\[2\], q0\[0\] |
123 |
+.*: ec00 0f06 vmov r6, r0, q0\[2\], q0\[0\] |
124 |
+.*: ec00 0f07 vmov r7, r0, q0\[2\], q0\[0\] |
125 |
+.*: ec00 0f08 vmov r8, r0, q0\[2\], q0\[0\] |
126 |
+.*: ec00 0f09 vmov r9, r0, q0\[2\], q0\[0\] |
127 |
+.*: ec00 0f0a vmov sl, r0, q0\[2\], q0\[0\] |
128 |
+.*: ec00 0f0b vmov fp, r0, q0\[2\], q0\[0\] |
129 |
+.*: ec00 0f0c vmov ip, r0, q0\[2\], q0\[0\] |
130 |
+.*: ec00 0f0e vmov lr, r0, q0\[2\], q0\[0\] |
131 |
+.*: ec01 0f00 vmov r0, r1, q0\[2\], q0\[0\] |
132 |
+.*: ec02 0f00 vmov r0, r2, q0\[2\], q0\[0\] |
133 |
+.*: ec03 0f00 vmov r0, r3, q0\[2\], q0\[0\] |
134 |
+.*: ec04 0f00 vmov r0, r4, q0\[2\], q0\[0\] |
135 |
+.*: ec05 0f00 vmov r0, r5, q0\[2\], q0\[0\] |
136 |
+.*: ec06 0f00 vmov r0, r6, q0\[2\], q0\[0\] |
137 |
+.*: ec07 0f00 vmov r0, r7, q0\[2\], q0\[0\] |
138 |
+.*: ec08 0f00 vmov r0, r8, q0\[2\], q0\[0\] |
139 |
+.*: ec09 0f00 vmov r0, r9, q0\[2\], q0\[0\] |
140 |
+.*: ec0a 0f00 vmov r0, sl, q0\[2\], q0\[0\] |
141 |
+.*: ec0b 0f00 vmov r0, fp, q0\[2\], q0\[0\] |
142 |
+.*: ec0c 0f00 vmov r0, ip, q0\[2\], q0\[0\] |
143 |
+.*: ec0e 0f00 vmov r0, lr, q0\[2\], q0\[0\] |
144 |
+.*: ec01 2f10 vmov r0, r1, q1\[3\], q1\[1\] |
145 |
+.*: ec01 4f10 vmov r0, r1, q2\[3\], q2\[1\] |
146 |
+.*: ec01 6f10 vmov r0, r1, q3\[3\], q3\[1\] |
147 |
+.*: ec01 8f10 vmov r0, r1, q4\[3\], q4\[1\] |
148 |
+.*: ec01 af10 vmov r0, r1, q5\[3\], q5\[1\] |
149 |
+.*: ec01 cf10 vmov r0, r1, q6\[3\], q6\[1\] |
150 |
+.*: ec01 ef10 vmov r0, r1, q7\[3\], q7\[1\] |
151 |
+.*: ec00 0f11 vmov r1, r0, q0\[3\], q0\[1\] |
152 |
+.*: ec00 0f12 vmov r2, r0, q0\[3\], q0\[1\] |
153 |
+.*: ec00 0f13 vmov r3, r0, q0\[3\], q0\[1\] |
154 |
+.*: ec00 0f14 vmov r4, r0, q0\[3\], q0\[1\] |
155 |
+.*: ec00 0f15 vmov r5, r0, q0\[3\], q0\[1\] |
156 |
+.*: ec00 0f16 vmov r6, r0, q0\[3\], q0\[1\] |
157 |
+.*: ec00 0f17 vmov r7, r0, q0\[3\], q0\[1\] |
158 |
+.*: ec00 0f18 vmov r8, r0, q0\[3\], q0\[1\] |
159 |
+.*: ec00 0f19 vmov r9, r0, q0\[3\], q0\[1\] |
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+.*: ec00 0f1a vmov sl, r0, q0\[3\], q0\[1\] |
161 |
+.*: ec00 0f1b vmov fp, r0, q0\[3\], q0\[1\] |
162 |
+.*: ec00 0f1c vmov ip, r0, q0\[3\], q0\[1\] |
163 |
+.*: ec00 0f1e vmov lr, r0, q0\[3\], q0\[1\] |
164 |
+.*: ec01 0f10 vmov r0, r1, q0\[3\], q0\[1\] |
165 |
+.*: ec02 0f10 vmov r0, r2, q0\[3\], q0\[1\] |
166 |
+.*: ec03 0f10 vmov r0, r3, q0\[3\], q0\[1\] |
167 |
+.*: ec04 0f10 vmov r0, r4, q0\[3\], q0\[1\] |
168 |
+.*: ec05 0f10 vmov r0, r5, q0\[3\], q0\[1\] |
169 |
+.*: ec06 0f10 vmov r0, r6, q0\[3\], q0\[1\] |
170 |
+.*: ec07 0f10 vmov r0, r7, q0\[3\], q0\[1\] |
171 |
+.*: ec08 0f10 vmov r0, r8, q0\[3\], q0\[1\] |
172 |
+.*: ec09 0f10 vmov r0, r9, q0\[3\], q0\[1\] |
173 |
+.*: ec0a 0f10 vmov r0, sl, q0\[3\], q0\[1\] |
174 |
+.*: ec0b 0f10 vmov r0, fp, q0\[3\], q0\[1\] |
175 |
+.*: ec0c 0f10 vmov r0, ip, q0\[3\], q0\[1\] |
176 |
+.*: ec0e 0f10 vmov r0, lr, q0\[3\], q0\[1\] |
177 |
+.*: ec11 2f00 vmov q1\[2\], q1\[0\], r0, r1 |
178 |
+.*: ec11 4f00 vmov q2\[2\], q2\[0\], r0, r1 |
179 |
+.*: ec11 6f00 vmov q3\[2\], q3\[0\], r0, r1 |
180 |
+.*: ec11 8f00 vmov q4\[2\], q4\[0\], r0, r1 |
181 |
+.*: ec11 af00 vmov q5\[2\], q5\[0\], r0, r1 |
182 |
+.*: ec11 cf00 vmov q6\[2\], q6\[0\], r0, r1 |
183 |
+.*: ec11 ef00 vmov q7\[2\], q7\[0\], r0, r1 |
184 |
+.*: ec10 0f00 vmov q0\[2\], q0\[0\], r0, r0 |
185 |
+.*: ec10 0f01 vmov q0\[2\], q0\[0\], r1, r0 |
186 |
+.*: ec10 0f02 vmov q0\[2\], q0\[0\], r2, r0 |
187 |
+.*: ec10 0f03 vmov q0\[2\], q0\[0\], r3, r0 |
188 |
+.*: ec10 0f04 vmov q0\[2\], q0\[0\], r4, r0 |
189 |
+.*: ec10 0f05 vmov q0\[2\], q0\[0\], r5, r0 |
190 |
+.*: ec10 0f06 vmov q0\[2\], q0\[0\], r6, r0 |
191 |
+.*: ec10 0f07 vmov q0\[2\], q0\[0\], r7, r0 |
192 |
+.*: ec10 0f08 vmov q0\[2\], q0\[0\], r8, r0 |
193 |
+.*: ec10 0f09 vmov q0\[2\], q0\[0\], r9, r0 |
194 |
+.*: ec10 0f0a vmov q0\[2\], q0\[0\], sl, r0 |
195 |
+.*: ec10 0f0b vmov q0\[2\], q0\[0\], fp, r0 |
196 |
+.*: ec10 0f0c vmov q0\[2\], q0\[0\], ip, r0 |
197 |
+.*: ec10 0f0e vmov q0\[2\], q0\[0\], lr, r0 |
198 |
+.*: ec11 0f00 vmov q0\[2\], q0\[0\], r0, r1 |
199 |
+.*: ec12 0f00 vmov q0\[2\], q0\[0\], r0, r2 |
200 |
+.*: ec13 0f00 vmov q0\[2\], q0\[0\], r0, r3 |
201 |
+.*: ec14 0f00 vmov q0\[2\], q0\[0\], r0, r4 |
202 |
+.*: ec15 0f00 vmov q0\[2\], q0\[0\], r0, r5 |
203 |
+.*: ec16 0f00 vmov q0\[2\], q0\[0\], r0, r6 |
204 |
+.*: ec17 0f00 vmov q0\[2\], q0\[0\], r0, r7 |
205 |
+.*: ec18 0f00 vmov q0\[2\], q0\[0\], r0, r8 |
206 |
+.*: ec19 0f00 vmov q0\[2\], q0\[0\], r0, r9 |
207 |
+.*: ec1a 0f00 vmov q0\[2\], q0\[0\], r0, sl |
208 |
+.*: ec1b 0f00 vmov q0\[2\], q0\[0\], r0, fp |
209 |
+.*: ec1c 0f00 vmov q0\[2\], q0\[0\], r0, ip |
210 |
+.*: ec1e 0f00 vmov q0\[2\], q0\[0\], r0, lr |
211 |
+.*: ec11 0f01 vmov q0\[2\], q0\[0\], r1, r1 |
212 |
+.*: ec12 0f02 vmov q0\[2\], q0\[0\], r2, r2 |
213 |
+.*: ec13 0f03 vmov q0\[2\], q0\[0\], r3, r3 |
214 |
+.*: ec14 0f04 vmov q0\[2\], q0\[0\], r4, r4 |
215 |
+.*: ec15 0f05 vmov q0\[2\], q0\[0\], r5, r5 |
216 |
+.*: ec16 0f06 vmov q0\[2\], q0\[0\], r6, r6 |
217 |
+.*: ec17 0f07 vmov q0\[2\], q0\[0\], r7, r7 |
218 |
+.*: ec18 0f08 vmov q0\[2\], q0\[0\], r8, r8 |
219 |
+.*: ec19 0f09 vmov q0\[2\], q0\[0\], r9, r9 |
220 |
+.*: ec1a 0f0a vmov q0\[2\], q0\[0\], sl, sl |
221 |
+.*: ec1b 0f0b vmov q0\[2\], q0\[0\], fp, fp |
222 |
+.*: ec1c 0f0c vmov q0\[2\], q0\[0\], ip, ip |
223 |
+.*: ec1e 0f0e vmov q0\[2\], q0\[0\], lr, lr |
224 |
+.*: ec11 2f10 vmov q1\[3\], q1\[1\], r0, r1 |
225 |
+.*: ec11 4f10 vmov q2\[3\], q2\[1\], r0, r1 |
226 |
+.*: ec11 6f10 vmov q3\[3\], q3\[1\], r0, r1 |
227 |
+.*: ec11 8f10 vmov q4\[3\], q4\[1\], r0, r1 |
228 |
+.*: ec11 af10 vmov q5\[3\], q5\[1\], r0, r1 |
229 |
+.*: ec11 cf10 vmov q6\[3\], q6\[1\], r0, r1 |
230 |
+.*: ec11 ef10 vmov q7\[3\], q7\[1\], r0, r1 |
231 |
+.*: ec10 0f10 vmov q0\[3\], q0\[1\], r0, r0 |
232 |
+.*: ec10 0f11 vmov q0\[3\], q0\[1\], r1, r0 |
233 |
+.*: ec10 0f12 vmov q0\[3\], q0\[1\], r2, r0 |
234 |
+.*: ec10 0f13 vmov q0\[3\], q0\[1\], r3, r0 |
235 |
+.*: ec10 0f14 vmov q0\[3\], q0\[1\], r4, r0 |
236 |
+.*: ec10 0f15 vmov q0\[3\], q0\[1\], r5, r0 |
237 |
+.*: ec10 0f16 vmov q0\[3\], q0\[1\], r6, r0 |
238 |
+.*: ec10 0f17 vmov q0\[3\], q0\[1\], r7, r0 |
239 |
+.*: ec10 0f18 vmov q0\[3\], q0\[1\], r8, r0 |
240 |
+.*: ec10 0f19 vmov q0\[3\], q0\[1\], r9, r0 |
241 |
+.*: ec10 0f1a vmov q0\[3\], q0\[1\], sl, r0 |
242 |
+.*: ec10 0f1b vmov q0\[3\], q0\[1\], fp, r0 |
243 |
+.*: ec10 0f1c vmov q0\[3\], q0\[1\], ip, r0 |
244 |
+.*: ec10 0f1e vmov q0\[3\], q0\[1\], lr, r0 |
245 |
+.*: ec11 0f10 vmov q0\[3\], q0\[1\], r0, r1 |
246 |
+.*: ec12 0f10 vmov q0\[3\], q0\[1\], r0, r2 |
247 |
+.*: ec13 0f10 vmov q0\[3\], q0\[1\], r0, r3 |
248 |
+.*: ec14 0f10 vmov q0\[3\], q0\[1\], r0, r4 |
249 |
+.*: ec15 0f10 vmov q0\[3\], q0\[1\], r0, r5 |
250 |
+.*: ec16 0f10 vmov q0\[3\], q0\[1\], r0, r6 |
251 |
+.*: ec17 0f10 vmov q0\[3\], q0\[1\], r0, r7 |
252 |
+.*: ec18 0f10 vmov q0\[3\], q0\[1\], r0, r8 |
253 |
+.*: ec19 0f10 vmov q0\[3\], q0\[1\], r0, r9 |
254 |
+.*: ec1a 0f10 vmov q0\[3\], q0\[1\], r0, sl |
255 |
+.*: ec1b 0f10 vmov q0\[3\], q0\[1\], r0, fp |
256 |
+.*: ec1c 0f10 vmov q0\[3\], q0\[1\], r0, ip |
257 |
+.*: ec1e 0f10 vmov q0\[3\], q0\[1\], r0, lr |
258 |
+.*: ec11 0f11 vmov q0\[3\], q0\[1\], r1, r1 |
259 |
+.*: ec12 0f12 vmov q0\[3\], q0\[1\], r2, r2 |
260 |
+.*: ec13 0f13 vmov q0\[3\], q0\[1\], r3, r3 |
261 |
+.*: ec14 0f14 vmov q0\[3\], q0\[1\], r4, r4 |
262 |
+.*: ec15 0f15 vmov q0\[3\], q0\[1\], r5, r5 |
263 |
+.*: ec16 0f16 vmov q0\[3\], q0\[1\], r6, r6 |
264 |
+.*: ec17 0f17 vmov q0\[3\], q0\[1\], r7, r7 |
265 |
+.*: ec18 0f18 vmov q0\[3\], q0\[1\], r8, r8 |
266 |
+.*: ec19 0f19 vmov q0\[3\], q0\[1\], r9, r9 |
267 |
+.*: ec1a 0f1a vmov q0\[3\], q0\[1\], sl, sl |
268 |
+.*: ec1b 0f1b vmov q0\[3\], q0\[1\], fp, fp |
269 |
+.*: ec1c 0f1c vmov q0\[3\], q0\[1\], ip, ip |
270 |
+.*: ec1e 0f1e vmov q0\[3\], q0\[1\], lr, lr |
271 |
diff --git gas/testsuite/gas/arm/mve-vmov-3.s gas/testsuite/gas/arm/mve-vmov-3.s |
272 |
new file mode 100644 |
273 |
index 00000000000..caf09576acd |
274 |
--- /dev/null |
275 |
+++ gas/testsuite/gas/arm/mve-vmov-3.s |
276 |
@@ -0,0 +1,160 @@ |
277 |
+vmov r0, r1, q1[2], q1[0] |
278 |
+vmov r0, r1, q2[2], q2[0] |
279 |
+vmov r0, r1, q3[2], q3[0] |
280 |
+vmov r0, r1, q4[2], q4[0] |
281 |
+vmov r0, r1, q5[2], q5[0] |
282 |
+vmov r0, r1, q6[2], q6[0] |
283 |
+vmov r0, r1, q7[2], q7[0] |
284 |
+vmov r1, r0, q0[2], q0[0] |
285 |
+vmov r2, r0, q0[2], q0[0] |
286 |
+vmov r3, r0, q0[2], q0[0] |
287 |
+vmov r4, r0, q0[2], q0[0] |
288 |
+vmov r5, r0, q0[2], q0[0] |
289 |
+vmov r6, r0, q0[2], q0[0] |
290 |
+vmov r7, r0, q0[2], q0[0] |
291 |
+vmov r8, r0, q0[2], q0[0] |
292 |
+vmov r9, r0, q0[2], q0[0] |
293 |
+vmov sl, r0, q0[2], q0[0] |
294 |
+vmov fp, r0, q0[2], q0[0] |
295 |
+vmov ip, r0, q0[2], q0[0] |
296 |
+vmov lr, r0, q0[2], q0[0] |
297 |
+vmov r0, r1, q0[2], q0[0] |
298 |
+vmov r0, r2, q0[2], q0[0] |
299 |
+vmov r0, r3, q0[2], q0[0] |
300 |
+vmov r0, r4, q0[2], q0[0] |
301 |
+vmov r0, r5, q0[2], q0[0] |
302 |
+vmov r0, r6, q0[2], q0[0] |
303 |
+vmov r0, r7, q0[2], q0[0] |
304 |
+vmov r0, r8, q0[2], q0[0] |
305 |
+vmov r0, r9, q0[2], q0[0] |
306 |
+vmov r0, sl, q0[2], q0[0] |
307 |
+vmov r0, fp, q0[2], q0[0] |
308 |
+vmov r0, ip, q0[2], q0[0] |
309 |
+vmov r0, lr, q0[2], q0[0] |
310 |
+vmov r0, r1, q1[3], q1[1] |
311 |
+vmov r0, r1, q2[3], q2[1] |
312 |
+vmov r0, r1, q3[3], q3[1] |
313 |
+vmov r0, r1, q4[3], q4[1] |
314 |
+vmov r0, r1, q5[3], q5[1] |
315 |
+vmov r0, r1, q6[3], q6[1] |
316 |
+vmov r0, r1, q7[3], q7[1] |
317 |
+vmov r1, r0, q0[3], q0[1] |
318 |
+vmov r2, r0, q0[3], q0[1] |
319 |
+vmov r3, r0, q0[3], q0[1] |
320 |
+vmov r4, r0, q0[3], q0[1] |
321 |
+vmov r5, r0, q0[3], q0[1] |
322 |
+vmov r6, r0, q0[3], q0[1] |
323 |
+vmov r7, r0, q0[3], q0[1] |
324 |
+vmov r8, r0, q0[3], q0[1] |
325 |
+vmov r9, r0, q0[3], q0[1] |
326 |
+vmov sl, r0, q0[3], q0[1] |
327 |
+vmov fp, r0, q0[3], q0[1] |
328 |
+vmov ip, r0, q0[3], q0[1] |
329 |
+vmov lr, r0, q0[3], q0[1] |
330 |
+vmov r0, r1, q0[3], q0[1] |
331 |
+vmov r0, r2, q0[3], q0[1] |
332 |
+vmov r0, r3, q0[3], q0[1] |
333 |
+vmov r0, r4, q0[3], q0[1] |
334 |
+vmov r0, r5, q0[3], q0[1] |
335 |
+vmov r0, r6, q0[3], q0[1] |
336 |
+vmov r0, r7, q0[3], q0[1] |
337 |
+vmov r0, r8, q0[3], q0[1] |
338 |
+vmov r0, r9, q0[3], q0[1] |
339 |
+vmov r0, sl, q0[3], q0[1] |
340 |
+vmov r0, fp, q0[3], q0[1] |
341 |
+vmov r0, ip, q0[3], q0[1] |
342 |
+vmov r0, lr, q0[3], q0[1] |
343 |
+vmov q1[2], q1[0], r0, r1 |
344 |
+vmov q2[2], q2[0], r0, r1 |
345 |
+vmov q3[2], q3[0], r0, r1 |
346 |
+vmov q4[2], q4[0], r0, r1 |
347 |
+vmov q5[2], q5[0], r0, r1 |
348 |
+vmov q6[2], q6[0], r0, r1 |
349 |
+vmov q7[2], q7[0], r0, r1 |
350 |
+vmov q0[2], q0[0], r0, r0 |
351 |
+vmov q0[2], q0[0], r1, r0 |
352 |
+vmov q0[2], q0[0], r2, r0 |
353 |
+vmov q0[2], q0[0], r3, r0 |
354 |
+vmov q0[2], q0[0], r4, r0 |
355 |
+vmov q0[2], q0[0], r5, r0 |
356 |
+vmov q0[2], q0[0], r6, r0 |
357 |
+vmov q0[2], q0[0], r7, r0 |
358 |
+vmov q0[2], q0[0], r8, r0 |
359 |
+vmov q0[2], q0[0], r9, r0 |
360 |
+vmov q0[2], q0[0], sl, r0 |
361 |
+vmov q0[2], q0[0], fp, r0 |
362 |
+vmov q0[2], q0[0], ip, r0 |
363 |
+vmov q0[2], q0[0], lr, r0 |
364 |
+vmov q0[2], q0[0], r0, r1 |
365 |
+vmov q0[2], q0[0], r0, r2 |
366 |
+vmov q0[2], q0[0], r0, r3 |
367 |
+vmov q0[2], q0[0], r0, r4 |
368 |
+vmov q0[2], q0[0], r0, r5 |
369 |
+vmov q0[2], q0[0], r0, r6 |
370 |
+vmov q0[2], q0[0], r0, r7 |
371 |
+vmov q0[2], q0[0], r0, r8 |
372 |
+vmov q0[2], q0[0], r0, r9 |
373 |
+vmov q0[2], q0[0], r0, sl |
374 |
+vmov q0[2], q0[0], r0, fp |
375 |
+vmov q0[2], q0[0], r0, ip |
376 |
+vmov q0[2], q0[0], r0, lr |
377 |
+vmov q0[2], q0[0], r1, r1 |
378 |
+vmov q0[2], q0[0], r2, r2 |
379 |
+vmov q0[2], q0[0], r3, r3 |
380 |
+vmov q0[2], q0[0], r4, r4 |
381 |
+vmov q0[2], q0[0], r5, r5 |
382 |
+vmov q0[2], q0[0], r6, r6 |
383 |
+vmov q0[2], q0[0], r7, r7 |
384 |
+vmov q0[2], q0[0], r8, r8 |
385 |
+vmov q0[2], q0[0], r9, r9 |
386 |
+vmov q0[2], q0[0], sl, sl |
387 |
+vmov q0[2], q0[0], fp, fp |
388 |
+vmov q0[2], q0[0], ip, ip |
389 |
+vmov q0[2], q0[0], lr, lr |
390 |
+vmov q1[3], q1[1], r0, r1 |
391 |
+vmov q2[3], q2[1], r0, r1 |
392 |
+vmov q3[3], q3[1], r0, r1 |
393 |
+vmov q4[3], q4[1], r0, r1 |
394 |
+vmov q5[3], q5[1], r0, r1 |
395 |
+vmov q6[3], q6[1], r0, r1 |
396 |
+vmov q7[3], q7[1], r0, r1 |
397 |
+vmov q0[3], q0[1], r0, r0 |
398 |
+vmov q0[3], q0[1], r1, r0 |
399 |
+vmov q0[3], q0[1], r2, r0 |
400 |
+vmov q0[3], q0[1], r3, r0 |
401 |
+vmov q0[3], q0[1], r4, r0 |
402 |
+vmov q0[3], q0[1], r5, r0 |
403 |
+vmov q0[3], q0[1], r6, r0 |
404 |
+vmov q0[3], q0[1], r7, r0 |
405 |
+vmov q0[3], q0[1], r8, r0 |
406 |
+vmov q0[3], q0[1], r9, r0 |
407 |
+vmov q0[3], q0[1], sl, r0 |
408 |
+vmov q0[3], q0[1], fp, r0 |
409 |
+vmov q0[3], q0[1], ip, r0 |
410 |
+vmov q0[3], q0[1], lr, r0 |
411 |
+vmov q0[3], q0[1], r0, r1 |
412 |
+vmov q0[3], q0[1], r0, r2 |
413 |
+vmov q0[3], q0[1], r0, r3 |
414 |
+vmov q0[3], q0[1], r0, r4 |
415 |
+vmov q0[3], q0[1], r0, r5 |
416 |
+vmov q0[3], q0[1], r0, r6 |
417 |
+vmov q0[3], q0[1], r0, r7 |
418 |
+vmov q0[3], q0[1], r0, r8 |
419 |
+vmov q0[3], q0[1], r0, r9 |
420 |
+vmov q0[3], q0[1], r0, sl |
421 |
+vmov q0[3], q0[1], r0, fp |
422 |
+vmov q0[3], q0[1], r0, ip |
423 |
+vmov q0[3], q0[1], r0, lr |
424 |
+vmov q0[3], q0[1], r1, r1 |
425 |
+vmov q0[3], q0[1], r2, r2 |
426 |
+vmov q0[3], q0[1], r3, r3 |
427 |
+vmov q0[3], q0[1], r4, r4 |
428 |
+vmov q0[3], q0[1], r5, r5 |
429 |
+vmov q0[3], q0[1], r6, r6 |
430 |
+vmov q0[3], q0[1], r7, r7 |
431 |
+vmov q0[3], q0[1], r8, r8 |
432 |
+vmov q0[3], q0[1], r9, r9 |
433 |
+vmov q0[3], q0[1], sl, sl |
434 |
+vmov q0[3], q0[1], fp, fp |
435 |
+vmov q0[3], q0[1], ip, ip |
436 |
+vmov q0[3], q0[1], lr, lr |
437 |
diff --git gas/testsuite/gas/arm/mve-vmov-bad-2.l gas/testsuite/gas/arm/mve-vmov-bad-2.l |
438 |
index 2f4bdc8293a..7c9226cf8ea 100644 |
439 |
--- gas/testsuite/gas/arm/mve-vmov-bad-2.l |
440 |
+++ gas/testsuite/gas/arm/mve-vmov-bad-2.l |
441 |
@@ -1,5 +1,5 @@ |
442 |
[^:]*: Assembler messages: |
443 |
-[^:]*:3: Error: General purpose registers may not be the same -- `vmov r0,r0,q0\[2\],q0\[0\]' |
444 |
+[^:]*:3: Error: Destination registers may not be the same -- `vmov r0,r0,q0\[2\],q0\[0\]' |
445 |
[^:]*:4: Error: r13 not allowed here -- `vmov sp,r0,q0\[2\],q0\[0\]' |
446 |
[^:]*:5: Error: r13 not allowed here -- `vmov r0,sp,q0\[2\],q0\[0\]' |
447 |
[^:]*:6: Error: r15 not allowed here -- `vmov pc,r0,q0\[2\],q0\[0\]' |
448 |
diff --git opcodes/ChangeLog opcodes/ChangeLog |
449 |
index ca9dff38798..43cd9bef661 100644 |
450 |
--- opcodes/ChangeLog |
451 |
+++ opcodes/ChangeLog |
452 |
@@ -1,3 +1,12 @@ |
453 |
+2021-05-19 Alex Coplan <alex.coplan@arm.com> |
454 |
+ |
455 |
+ * arm-dis.c (mve_opcodes): Fix disassembly of |
456 |
+ MVE_VMOV2_GP_TO_VEC_LANE when idx == 1. |
457 |
+ (is_mve_encoding_conflict): MVE vector loads should not match |
458 |
+ when P = W = 0. |
459 |
+ (is_mve_unpredictable): It's not unpredictable to use the same |
460 |
+ source register twice (for MVE_VMOV2_GP_TO_VEC_LANE). |
461 |
+ |
462 |
2021-04-09 Tejas Belagod <tejas.belagod@arm.com> |
463 |
|
464 |
Backported from mainline. |
465 |
diff --git opcodes/arm-dis.c opcodes/arm-dis.c |
466 |
index f16a5902479..97632693803 100644 |
467 |
--- opcodes/arm-dis.c |
468 |
+++ opcodes/arm-dis.c |
469 |
@@ -2959,7 +2959,7 @@ static const struct mopcode32 mve_opcodes[] = |
470 |
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
471 |
MVE_VMOV2_GP_TO_VEC_LANE, |
472 |
0xec100f10, 0xffb01ff0, |
473 |
- "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"}, |
474 |
+ "vmov%c\t%13-15,22Q[3], %13-15,22Q[1], %0-3r, %16-19r"}, |
475 |
|
476 |
/* Vector VMOV Vector lane to gpr. */ |
477 |
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
478 |
@@ -5727,6 +5727,9 @@ is_mve_encoding_conflict (unsigned long given, |
479 |
else |
480 |
return FALSE; |
481 |
|
482 |
+ case MVE_VLDRB_T1: |
483 |
+ case MVE_VLDRH_T2: |
484 |
+ case MVE_VLDRW_T7: |
485 |
case MVE_VSTRB_T5: |
486 |
case MVE_VSTRH_T6: |
487 |
case MVE_VSTRW_T7: |
488 |
@@ -6661,7 +6664,7 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn, |
489 |
*unpredictable_code = UNPRED_R15; |
490 |
return TRUE; |
491 |
} |
492 |
- else if (rt == rt2) |
493 |
+ else if (rt == rt2 && matched_insn != MVE_VMOV2_GP_TO_VEC_LANE) |
494 |
{ |
495 |
*unpredictable_code = UNPRED_GP_REGS_EQUAL; |
496 |
return TRUE; |
497 |
-- |
498 |
2.32.0 |
499 |
|