Attachment 148598 Details for Bug 194234 – Patch for the shared code -- every other non-core source file

[patch] Patch for the shared code -- every other non-core source file

shared_v2.patch (text/plain), 159.29 KB, created by Eric Joyner on 2014-10-23 22:51:46 UTC

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Creator: Eric Joyner

Created: 2014-10-23 22:51:46 UTC

Size: 159.29 KB

patch

obsolete

>Index: ixgbe_82598.c
>===================================================================
>--- ixgbe_82598.c	(revision 273551)
>+++ ixgbe_82598.c	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>@@ -38,6 +38,13 @@
> #include "ixgbe_common.h"
> #include "ixgbe_phy.h"
> 
>+#define IXGBE_82598_MAX_TX_QUEUES 32
>+#define IXGBE_82598_MAX_RX_QUEUES 64
>+#define IXGBE_82598_RAR_ENTRIES   16
>+#define IXGBE_82598_MC_TBL_SIZE  128
>+#define IXGBE_82598_VFT_TBL_SIZE 128
>+#define IXGBE_82598_RX_PB_SIZE   512
>+
> static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
> 					     ixgbe_link_speed *speed,
> 					     bool *autoneg);
>@@ -133,6 +140,7 @@
> 	mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;
> 	mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;
> 	mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598;
>+	mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82598;
> 
> 	/* RAR, Multicast, VLAN */
> 	mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
>@@ -144,12 +152,12 @@
> 	/* Flow Control */
> 	mac->ops.fc_enable = &ixgbe_fc_enable_82598;
> 
>-	mac->mcft_size		= 128;
>-	mac->vft_size		= 128;
>-	mac->num_rar_entries	= 16;
>-	mac->rx_pb_size		= 512;
>-	mac->max_tx_queues	= 32;
>-	mac->max_rx_queues	= 64;
>+	mac->mcft_size		= IXGBE_82598_MC_TBL_SIZE;
>+	mac->vft_size		= IXGBE_82598_VFT_TBL_SIZE;
>+	mac->num_rar_entries	= IXGBE_82598_RAR_ENTRIES;
>+	mac->rx_pb_size		= IXGBE_82598_RX_PB_SIZE;
>+	mac->max_rx_queues	= IXGBE_82598_MAX_RX_QUEUES;
>+	mac->max_tx_queues	= IXGBE_82598_MAX_TX_QUEUES;
> 	mac->max_msix_vectors	= ixgbe_get_pcie_msix_count_generic(hw);
> 
> 	/* SFP+ Module */
>@@ -1409,6 +1417,20 @@
> 	/* Setup Tx packet buffer sizes */
> 	for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
> 		IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
>+}
> 
>-	return;
>+/**
>+ *  ixgbe_enable_rx_dma_82598 - Enable the Rx DMA unit
>+ *  @hw: pointer to hardware structure
>+ *  @regval: register value to write to RXCTRL
>+ *
>+ *  Enables the Rx DMA unit
>+ **/
>+s32 ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, u32 regval)
>+{
>+	DEBUGFUNC("ixgbe_enable_rx_dma_82598");
>+
>+	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
>+
>+	return IXGBE_SUCCESS;
> }
>Index: ixgbe_82598.h
>===================================================================
>--- ixgbe_82598.h	(revision 273551)
>+++ ixgbe_82598.h	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2012, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>@@ -49,4 +49,5 @@
> s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw);
> void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw);
> void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw);
>+s32 ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, u32 regval);
> #endif /* _IXGBE_82598_H_ */
>Index: ixgbe_82599.c
>===================================================================
>--- ixgbe_82599.c	(revision 273551)
>+++ ixgbe_82599.c	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>@@ -38,6 +38,13 @@
> #include "ixgbe_common.h"
> #include "ixgbe_phy.h"
> 
>+#define IXGBE_82599_MAX_TX_QUEUES 128
>+#define IXGBE_82599_MAX_RX_QUEUES 128
>+#define IXGBE_82599_RAR_ENTRIES   128
>+#define IXGBE_82599_MC_TBL_SIZE   128
>+#define IXGBE_82599_VFT_TBL_SIZE  128
>+#define IXGBE_82599_RX_PB_SIZE	  512
>+
> static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
> 					 ixgbe_link_speed speed,
> 					 bool autoneg_wait_to_complete);
>@@ -46,26 +53,11 @@
> 				   u16 offset, u16 *data);
> static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
> 					  u16 words, u16 *data);
>+static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
>+					u8 dev_addr, u8 *data);
>+static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
>+					u8 dev_addr, u8 data);
> 
>-static bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
>-{
>-	u32 fwsm, manc, factps;
>-
>-	fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
>-	if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
>-		return FALSE;
>-
>-	manc = IXGBE_READ_REG(hw, IXGBE_MANC);
>-	if (!(manc & IXGBE_MANC_RCV_TCO_EN))
>-		return FALSE;
>-
>-	factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
>-	if (factps & IXGBE_FACTPS_MNGCG)
>-		return FALSE;
>-
>-	return TRUE;
>-}
>-
> void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
> {
> 	struct ixgbe_mac_info *mac = &hw->mac;
>@@ -77,7 +69,7 @@
> 	 * and MNG not enabled
> 	 */
> 	if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
>-	    !hw->mng_fw_enabled) {
>+	    !ixgbe_mng_enabled(hw)) {
> 		mac->ops.disable_tx_laser =
> 				       &ixgbe_disable_tx_laser_multispeed_fiber;
> 		mac->ops.enable_tx_laser =
>@@ -119,9 +111,27 @@
> 	struct ixgbe_mac_info *mac = &hw->mac;
> 	struct ixgbe_phy_info *phy = &hw->phy;
> 	s32 ret_val = IXGBE_SUCCESS;
>+	u32 esdp;
> 
> 	DEBUGFUNC("ixgbe_init_phy_ops_82599");
> 
>+	if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
>+		/* Store flag indicating I2C bus access control unit. */
>+		hw->phy.qsfp_shared_i2c_bus = TRUE;
>+
>+		/* Initialize access to QSFP+ I2C bus */
>+		esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
>+		esdp |= IXGBE_ESDP_SDP0_DIR;
>+		esdp &= ~IXGBE_ESDP_SDP1_DIR;
>+		esdp &= ~IXGBE_ESDP_SDP0;
>+		esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
>+		esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
>+		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
>+		IXGBE_WRITE_FLUSH(hw);
>+
>+		phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599;
>+		phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599;
>+	}
> 	/* Identify the PHY or SFP module */
> 	ret_val = phy->ops.identify(hw);
> 	if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
>@@ -139,7 +149,7 @@
> 				  &ixgbe_get_copper_link_capabilities_generic;
> 	}
> 
>-	/* Set necessary function pointers based on phy type */
>+	/* Set necessary function pointers based on PHY type */
> 	switch (hw->phy.type) {
> 	case ixgbe_phy_tn:
> 		phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
>@@ -158,7 +168,6 @@
> {
> 	s32 ret_val = IXGBE_SUCCESS;
> 	u16 list_offset, data_offset, data_value;
>-	bool got_lock = FALSE;
> 
> 	DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
> 
>@@ -191,36 +200,16 @@
> 
> 		/* Release the semaphore */
> 		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
>-		/* Delay obtaining semaphore again to allow FW access */
>+		/* Delay obtaining semaphore again to allow FW access
>+		 * prot_autoc_write uses the semaphore too.
>+		 */
> 		msec_delay(hw->eeprom.semaphore_delay);
> 
>-		/* Need SW/FW semaphore around AUTOC writes if LESM on,
>-		 * likewise reset_pipeline requires lock as it also writes
>-		 * AUTOC.
>-		 */
>-		if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
>-			ret_val = hw->mac.ops.acquire_swfw_sync(hw,
>-							IXGBE_GSSR_MAC_CSR_SM);
>-			if (ret_val != IXGBE_SUCCESS) {
>-				ret_val = IXGBE_ERR_SWFW_SYNC;
>-				goto setup_sfp_out;
>-			}
>-
>-			got_lock = TRUE;
>-		}
>-
> 		/* Restart DSP and set SFI mode */
>-		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((hw->mac.orig_autoc) |
>-				IXGBE_AUTOC_LMS_10G_SERIAL));
>-		hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
>-		ret_val = ixgbe_reset_pipeline_82599(hw);
>+		ret_val = hw->mac.ops.prot_autoc_write(hw,
>+			hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
>+			FALSE);
> 
>-		if (got_lock) {
>-			hw->mac.ops.release_swfw_sync(hw,
>-						      IXGBE_GSSR_MAC_CSR_SM);
>-			got_lock = FALSE;
>-		}
>-
> 		if (ret_val) {
> 			DEBUGOUT("sfp module setup not complete\n");
> 			ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
>@@ -243,6 +232,79 @@
> }
> 
> /**
>+ *  prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
>+ *  @hw: pointer to hardware structure
>+ *  @locked: Return the if we locked for this read.
>+ *  @reg_val: Value we read from AUTOC
>+ *
>+ *  For this part (82599) we need to wrap read-modify-writes with a possible
>+ *  FW/SW lock.  It is assumed this lock will be freed with the next
>+ *  prot_autoc_write_82599().
>+ */
>+s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
>+{
>+	s32 ret_val;
>+
>+	*locked = FALSE;
>+	 /* If LESM is on then we need to hold the SW/FW semaphore. */
>+	if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
>+		ret_val = hw->mac.ops.acquire_swfw_sync(hw,
>+					IXGBE_GSSR_MAC_CSR_SM);
>+		if (ret_val != IXGBE_SUCCESS)
>+			return IXGBE_ERR_SWFW_SYNC;
>+
>+		*locked = TRUE;
>+	}
>+
>+	*reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
>+	return IXGBE_SUCCESS;
>+}
>+
>+/**
>+ * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
>+ * @hw: pointer to hardware structure
>+ * @reg_val: value to write to AUTOC
>+ * @locked: bool to indicate whether the SW/FW lock was already taken by
>+ *           previous proc_autoc_read_82599.
>+ *
>+ * This part (82599) may need to hold the SW/FW lock around all writes to
>+ * AUTOC. Likewise after a write we need to do a pipeline reset.
>+ */
>+s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
>+{
>+	s32 ret_val = IXGBE_SUCCESS;
>+
>+	/* Blocked by MNG FW so bail */
>+	if (ixgbe_check_reset_blocked(hw))
>+		goto out;
>+
>+	/* We only need to get the lock if:
>+	 *  - We didn't do it already (in the read part of a read-modify-write)
>+	 *  - LESM is enabled.
>+	 */
>+	if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
>+		ret_val = hw->mac.ops.acquire_swfw_sync(hw,
>+					IXGBE_GSSR_MAC_CSR_SM);
>+		if (ret_val != IXGBE_SUCCESS)
>+			return IXGBE_ERR_SWFW_SYNC;
>+
>+		locked = TRUE;
>+	}
>+
>+	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
>+	ret_val = ixgbe_reset_pipeline_82599(hw);
>+
>+out:
>+	/* Free the SW/FW semaphore as we either grabbed it here or
>+	 * already had it when this function was called.
>+	 */
>+	if (locked)
>+		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
>+
>+	return ret_val;
>+}
>+
>+/**
>  *  ixgbe_init_ops_82599 - Inits func ptrs and MAC type
>  *  @hw: pointer to hardware structure
>  *
>@@ -283,6 +345,8 @@
> 	mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
> 	mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
> 	mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
>+	mac->ops.prot_autoc_read = &prot_autoc_read_82599;
>+	mac->ops.prot_autoc_write = &prot_autoc_write_82599;
> 
> 	/* RAR, Multicast, VLAN */
> 	mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
>@@ -304,12 +368,12 @@
> 	mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
> 	ixgbe_init_mac_link_ops_82599(hw);
> 
>-	mac->mcft_size		= 128;
>-	mac->vft_size		= 128;
>-	mac->num_rar_entries	= 128;
>-	mac->rx_pb_size		= 512;
>-	mac->max_tx_queues	= 128;
>-	mac->max_rx_queues	= 128;
>+	mac->mcft_size		= IXGBE_82599_MC_TBL_SIZE;
>+	mac->vft_size		= IXGBE_82599_VFT_TBL_SIZE;
>+	mac->num_rar_entries	= IXGBE_82599_RAR_ENTRIES;
>+	mac->rx_pb_size		= IXGBE_82599_RX_PB_SIZE;
>+	mac->max_rx_queues	= IXGBE_82599_MAX_RX_QUEUES;
>+	mac->max_tx_queues	= IXGBE_82599_MAX_TX_QUEUES;
> 	mac->max_msix_vectors	= ixgbe_get_pcie_msix_count_generic(hw);
> 
> 	mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
>@@ -327,9 +391,6 @@
> 
> 	mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
> 
>-	/* Cache if MNG FW is up */
>-	hw->mng_fw_enabled = ixgbe_mng_enabled(hw);
>-
> 	return ret_val;
> }
> 
>@@ -429,7 +490,14 @@
> 	if (hw->phy.multispeed_fiber) {
> 		*speed |= IXGBE_LINK_SPEED_10GB_FULL |
> 			  IXGBE_LINK_SPEED_1GB_FULL;
>-		*autoneg = TRUE;
>+
>+		/* QSFP must not enable full auto-negotiation
>+		 * Limited autoneg is enabled at 1G
>+		 */
>+		if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
>+			*autoneg = FALSE;
>+		else
>+			*autoneg = TRUE;
> 	}
> 
> out:
>@@ -482,6 +550,9 @@
> 	case IXGBE_DEV_ID_82599_T3_LOM:
> 		media_type = ixgbe_media_type_copper;
> 		break;
>+	case IXGBE_DEV_ID_82599_QSFP_SF_QP:
>+		media_type = ixgbe_media_type_fiber_qsfp;
>+		break;
> 	case IXGBE_DEV_ID_82599_BYPASS:
> 		media_type = ixgbe_media_type_fiber_fixed;
> 		hw->phy.multispeed_fiber = TRUE;
>@@ -503,14 +574,18 @@
>  **/
> void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
> {
>-	u32 autoc2_reg;
>+	u32 autoc2_reg, fwsm;
> 	u16 ee_ctrl_2 = 0;
> 
> 	DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
> 	ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
> 
>-	if (!hw->mng_fw_enabled && !hw->wol_enabled &&
>-		ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
>+	/* Check to see if MNG FW could be enabled */
>+	fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
>+
>+	if (((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) &&
>+	    !hw->wol_enabled &&
>+	    ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
> 		autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
> 		autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
> 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
>@@ -597,7 +672,11 @@
> {
> 	u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
> 
>-	/* Disable tx laser; allow 100us to go dark per spec */
>+	/* Blocked by MNG FW so bail */
>+	if (ixgbe_check_reset_blocked(hw))
>+		return;
>+
>+	/* Disable Tx laser; allow 100us to go dark per spec */
> 	esdp_reg |= IXGBE_ESDP_SDP3;
> 	IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
> 	IXGBE_WRITE_FLUSH(hw);
>@@ -616,7 +695,7 @@
> {
> 	u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
> 
>-	/* Enable tx laser; allow 100ms to light up */
>+	/* Enable Tx laser; allow 100ms to light up */
> 	esdp_reg &= ~IXGBE_ESDP_SDP3;
> 	IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
> 	IXGBE_WRITE_FLUSH(hw);
>@@ -630,7 +709,7 @@
>  *  When the driver changes the link speeds that it can support,
>  *  it sets autotry_restart to TRUE to indicate that we need to
>  *  initiate a new autotry session with the link partner.  To do
>- *  so, we set the speed then disable and re-enable the tx laser, to
>+ *  so, we set the speed then disable and re-enable the Tx laser, to
>  *  alert the link partner that it also needs to restart autotry on its
>  *  end.  This is consistent with TRUE clause 37 autoneg, which also
>  *  involves a loss of signal.
>@@ -639,6 +718,10 @@
> {
> 	DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
> 
>+	/* Blocked by MNG FW so bail */
>+	if (ixgbe_check_reset_blocked(hw))
>+		return;
>+
> 	if (hw->mac.autotry_restart) {
> 		ixgbe_disable_tx_laser_multispeed_fiber(hw);
> 		ixgbe_enable_tx_laser_multispeed_fiber(hw);
>@@ -683,7 +766,7 @@
> 		goto out;
> 	}
> 
>-	eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs;
>+	eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
> 
> 	status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
> 					    IXGBE_I2C_EEPROM_DEV_ADDR2,
>@@ -702,7 +785,7 @@
> 		goto out;
> 	}
> 
>-	eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs;
>+	eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
> 
> 	status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
> 					    IXGBE_I2C_EEPROM_DEV_ADDR2,
>@@ -761,13 +844,22 @@
> 			goto out;
> 
> 		/* Set the module link speed */
>-		if (hw->phy.media_type == ixgbe_media_type_fiber_fixed) {
>+		switch (hw->phy.media_type) {
>+		case ixgbe_media_type_fiber_fixed:
> 			ixgbe_set_fiber_fixed_speed(hw,
> 						    IXGBE_LINK_SPEED_10GB_FULL);
>-		} else {
>+			break;
>+		case ixgbe_media_type_fiber:
> 			esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
> 			IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
> 			IXGBE_WRITE_FLUSH(hw);
>+			break;
>+		case ixgbe_media_type_fiber_qsfp:
>+			/* QSFP module automatically detects MAC link speed */
>+			break;
>+		default:
>+			DEBUGOUT("Unexpected media type.\n");
>+			break;
> 		}
> 
> 		/* Allow module to change analog characteristics (1G->10G) */
>@@ -816,14 +908,23 @@
> 			goto out;
> 
> 		/* Set the module link speed */
>-		if (hw->phy.media_type == ixgbe_media_type_fiber_fixed) {
>+		switch (hw->phy.media_type) {
>+		case ixgbe_media_type_fiber_fixed:
> 			ixgbe_set_fiber_fixed_speed(hw,
> 						    IXGBE_LINK_SPEED_1GB_FULL);
>-		} else {
>+			break;
>+		case ixgbe_media_type_fiber:
> 			esdp_reg &= ~IXGBE_ESDP_SDP5;
> 			esdp_reg |= IXGBE_ESDP_SDP5_DIR;
> 			IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
> 			IXGBE_WRITE_FLUSH(hw);
>+			break;
>+		case ixgbe_media_type_fiber_qsfp:
>+			/* QSFP module automatically detects link speed */
>+			break;
>+		default:
>+			DEBUGOUT("Unexpected media type.\n");
>+			break;
> 		}
> 
> 		/* Allow module to change analog characteristics (10G->1G) */
>@@ -835,7 +936,7 @@
> 		if (status != IXGBE_SUCCESS)
> 			return status;
> 
>-		/* Flap the tx laser if it has not already been done */
>+		/* Flap the Tx laser if it has not already been done */
> 		ixgbe_flap_tx_laser(hw);
> 
> 		/* Wait for the link partner to also set speed */
>@@ -998,14 +1099,15 @@
> {
> 	bool autoneg = FALSE;
> 	s32 status = IXGBE_SUCCESS;
>-	u32 autoc, pma_pmd_1g, link_mode, start_autoc;
>+	u32 pma_pmd_1g, link_mode;
>+	u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */
>+	u32 orig_autoc = 0; /* holds the cached value of AUTOC register */
>+	u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */
> 	u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
>-	u32 orig_autoc = 0;
> 	u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
> 	u32 links_reg;
> 	u32 i;
> 	ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
>-	bool got_lock = FALSE;
> 
> 	DEBUGFUNC("ixgbe_setup_mac_link_82599");
> 
>@@ -1023,12 +1125,10 @@
> 
> 	/* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
> 	if (hw->mac.orig_link_settings_stored)
>-		autoc = hw->mac.orig_autoc;
>+		orig_autoc = hw->mac.orig_autoc;
> 	else
>-		autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
>+		orig_autoc = autoc;
> 
>-	orig_autoc = autoc;
>-	start_autoc = hw->mac.cached_autoc;
> 	link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
> 	pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
> 
>@@ -1061,7 +1161,7 @@
> 		if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
> 		    (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
> 			autoc &= ~IXGBE_AUTOC_LMS_MASK;
>-			if (autoneg)
>+			if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel)
> 				autoc |= IXGBE_AUTOC_LMS_1G_AN;
> 			else
> 				autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
>@@ -1068,33 +1168,12 @@
> 		}
> 	}
> 
>-	if (autoc != start_autoc) {
>-		/* Need SW/FW semaphore around AUTOC writes if LESM is on,
>-		 * likewise reset_pipeline requires us to hold this lock as
>-		 * it also writes to AUTOC.
>-		 */
>-		if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
>-			status = hw->mac.ops.acquire_swfw_sync(hw,
>-							IXGBE_GSSR_MAC_CSR_SM);
>-			if (status != IXGBE_SUCCESS) {
>-				status = IXGBE_ERR_SWFW_SYNC;
>-				goto out;
>-			}
>-
>-			got_lock = TRUE;
>-		}
>-
>+	if (autoc != current_autoc) {
> 		/* Restart link */
>-		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
>-		hw->mac.cached_autoc = autoc;
>-		ixgbe_reset_pipeline_82599(hw);
>+		status = hw->mac.ops.prot_autoc_write(hw, autoc, FALSE);
>+		if (status != IXGBE_SUCCESS)
>+			goto out;
> 
>-		if (got_lock) {
>-			hw->mac.ops.release_swfw_sync(hw,
>-						      IXGBE_GSSR_MAC_CSR_SM);
>-			got_lock = FALSE;
>-		}
>-
> 		/* Only poll for autoneg to complete if specified to do so */
> 		if (autoneg_wait_to_complete) {
> 			if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
>@@ -1161,7 +1240,8 @@
> {
> 	ixgbe_link_speed link_speed;
> 	s32 status;
>-	u32 ctrl, i, autoc2;
>+	u32 ctrl = 0;
>+	u32 i, autoc, autoc2;
> 	u32 curr_lms;
> 	bool link_up = FALSE;
> 
>@@ -1197,11 +1277,7 @@
> 		hw->phy.ops.reset(hw);
> 
> 	/* remember AUTOC from before we reset */
>-	if (hw->mac.cached_autoc)
>-		curr_lms = hw->mac.cached_autoc & IXGBE_AUTOC_LMS_MASK;
>-	else
>-		curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) &
>-					  IXGBE_AUTOC_LMS_MASK;
>+	curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
> 
> mac_reset_top:
> 	/*
>@@ -1221,7 +1297,7 @@
> 	IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
> 	IXGBE_WRITE_FLUSH(hw);
> 
>-	/* Poll for reset bit to self-clear indicating reset is complete */
>+	/* Poll for reset bit to self-clear meaning reset is complete */
> 	for (i = 0; i < 10; i++) {
> 		usec_delay(1);
> 		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
>@@ -1238,8 +1314,8 @@
> 
> 	/*
> 	 * Double resets are required for recovery from certain error
>-	 * conditions.  Between resets, it is necessary to stall to allow time
>-	 * for any pending HW events to complete.
>+	 * conditions.  Between resets, it is necessary to stall to
>+	 * allow time for any pending HW events to complete.
> 	 */
> 	if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
> 		hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
>@@ -1251,7 +1327,7 @@
> 	 * stored off yet.  Otherwise restore the stored original
> 	 * values since the reset operation sets back to defaults.
> 	 */
>-	hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
>+	autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
> 	autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
> 
> 	/* Enable link if disabled in NVM */
>@@ -1262,7 +1338,7 @@
> 	}
> 
> 	if (hw->mac.orig_link_settings_stored == FALSE) {
>-		hw->mac.orig_autoc = hw->mac.cached_autoc;
>+		hw->mac.orig_autoc = autoc;
> 		hw->mac.orig_autoc2 = autoc2;
> 		hw->mac.orig_link_settings_stored = TRUE;
> 	} else {
>@@ -1273,36 +1349,18 @@
> 		 * Likewise if we support WoL we don't want change the
> 		 * LMS state.
> 		 */
>-		if ((hw->phy.multispeed_fiber && hw->mng_fw_enabled) ||
>+		if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
> 		    hw->wol_enabled)
> 			hw->mac.orig_autoc =
> 				(hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
> 				curr_lms;
> 
>-		if (hw->mac.cached_autoc != hw->mac.orig_autoc) {
>-			/* Need SW/FW semaphore around AUTOC writes if LESM is
>-			 * on, likewise reset_pipeline requires us to hold
>-			 * this lock as it also writes to AUTOC.
>-			 */
>-			bool got_lock = FALSE;
>-			if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
>-				status = hw->mac.ops.acquire_swfw_sync(hw,
>-							IXGBE_GSSR_MAC_CSR_SM);
>-				if (status != IXGBE_SUCCESS) {
>-					status = IXGBE_ERR_SWFW_SYNC;
>-					goto reset_hw_out;
>-				}
>-
>-				got_lock = TRUE;
>-			}
>-
>-			IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
>-			hw->mac.cached_autoc = hw->mac.orig_autoc;
>-			ixgbe_reset_pipeline_82599(hw);
>-
>-			if (got_lock)
>-				hw->mac.ops.release_swfw_sync(hw,
>-						      IXGBE_GSSR_MAC_CSR_SM);
>+		if (autoc != hw->mac.orig_autoc) {
>+			status = hw->mac.ops.prot_autoc_write(hw,
>+							hw->mac.orig_autoc,
>+							FALSE);
>+			if (status != IXGBE_SUCCESS)
>+				goto reset_hw_out;
> 		}
> 
> 		if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
>@@ -1349,13 +1407,34 @@
> }
> 
> /**
>+ * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
>+ * @hw: pointer to hardware structure
>+ * @fdircmd: current value of FDIRCMD register
>+ */
>+static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)
>+{
>+	int i;
>+
>+	for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
>+		*fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
>+		if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
>+			return IXGBE_SUCCESS;
>+		usec_delay(10);
>+	}
>+
>+	return IXGBE_ERR_FDIR_CMD_INCOMPLETE;
>+}
>+
>+/**
>  *  ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
>  *  @hw: pointer to hardware structure
>  **/
> s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
> {
>+	s32 err;
> 	int i;
> 	u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
>+	u32 fdircmd;
> 	fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
> 
> 	DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
>@@ -1364,17 +1443,11 @@
> 	 * Before starting reinitialization process,
> 	 * FDIRCMD.CMD must be zero.
> 	 */
>-	for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
>-		if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
>-		      IXGBE_FDIRCMD_CMD_MASK))
>-			break;
>-		usec_delay(10);
>+	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
>+	if (err) {
>+		DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n");
>+		return err;
> 	}
>-	if (i >= IXGBE_FDIRCMD_CMD_POLL) {
>-		DEBUGOUT("Flow Director previous command isn't complete, "
>-			 "aborting table re-initialization.\n");
>-		return IXGBE_ERR_FDIR_REINIT_FAILED;
>-	}
> 
> 	IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
> 	IXGBE_WRITE_FLUSH(hw);
>@@ -1497,9 +1570,12 @@
>  *  @hw: pointer to hardware structure
>  *  @fdirctrl: value to write to flow director control register, initially
>  *	     contains just the value of the Rx packet buffer allocation
>+ *  @cloud_mode: TRUE - cloud mode, FALSE - other mode
>  **/
>-s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
>+s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
>+			bool cloud_mode)
> {
>+	UNREFERENCED_1PARAMETER(cloud_mode);
> 	DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
> 
> 	/*
>@@ -1518,6 +1594,7 @@
> 		    (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
> 		    (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
> 
>+
> 	/* write hashes and fdirctrl register, poll for completion */
> 	ixgbe_fdir_enable_82599(hw, fdirctrl);
> 
>@@ -1546,7 +1623,7 @@
> 		bucket_hash ^= hi_hash_dword >> n; \
> 	else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
> 		sig_hash ^= hi_hash_dword << (16 - n); \
>-} while (0);
>+} while (0)
> 
> /**
>  *  ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
>@@ -1553,7 +1630,7 @@
>  *  @stream: input bitstream to compute the hash on
>  *
>  *  This function is almost identical to the function above but contains
>- *  several optomizations such as unwinding all of the loops, letting the
>+ *  several optimizations such as unwinding all of the loops, letting the
>  *  compiler work out all of the conditional ifs since the keys are static
>  *  defines, and computing two keys at once since the hashed dword stream
>  *  will be the same for both keys.
>@@ -1582,7 +1659,7 @@
> 	/*
> 	 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
> 	 * delay this because bit 0 of the stream should not be processed
>-	 * so we do not add the vlan until after bit 0 was processed
>+	 * so we do not add the VLAN until after bit 0 was processed
> 	 */
> 	lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
> 
>@@ -1626,8 +1703,10 @@
> 					  union ixgbe_atr_hash_dword common,
> 					  u8 queue)
> {
>-	u64  fdirhashcmd;
>-	u32  fdircmd;
>+	u64 fdirhashcmd;
>+	u8 flow_type;
>+	u32 fdircmd;
>+	s32 err;
> 
> 	DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
> 
>@@ -1634,8 +1713,11 @@
> 	/*
> 	 * Get the flow_type in order to program FDIRCMD properly
> 	 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
>+	 * fifth is FDIRCMD.TUNNEL_FILTER
> 	 */
>-	switch (input.formatted.flow_type) {
>+	flow_type = input.formatted.flow_type &
>+		    (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1);
>+	switch (flow_type) {
> 	case IXGBE_ATR_FLOW_TYPE_TCPV4:
> 	case IXGBE_ATR_FLOW_TYPE_UDPV4:
> 	case IXGBE_ATR_FLOW_TYPE_SCTPV4:
>@@ -1651,7 +1733,7 @@
> 	/* configure FDIRCMD register */
> 	fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
> 		  IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
>-	fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
>+	fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
> 	fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
> 
> 	/*
>@@ -1662,6 +1744,12 @@
> 	fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
> 	IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
> 
>+	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
>+	if (err) {
>+		DEBUGOUT("Flow Director command did not complete!\n");
>+		return err;
>+	}
>+
> 	DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
> 
> 	return IXGBE_SUCCESS;
>@@ -1674,7 +1762,7 @@
> 		bucket_hash ^= lo_hash_dword >> n; \
> 	if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
> 		bucket_hash ^= hi_hash_dword >> n; \
>-} while (0);
>+} while (0)
> 
> /**
>  *  ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
>@@ -1681,7 +1769,7 @@
>  *  @atr_input: input bitstream to compute the hash on
>  *  @input_mask: mask for the input bitstream
>  *
>- *  This function serves two main purposes.  First it applys the input_mask
>+ *  This function serves two main purposes.  First it applies the input_mask
>  *  to the atr_input resulting in a cleaned up atr_input data stream.
>  *  Secondly it computes the hash and stores it in the bkt_hash field at
>  *  the end of the input byte stream.  This way it will be available for
>@@ -1693,34 +1781,20 @@
> 
> 	u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
> 	u32 bucket_hash = 0;
>+	u32 hi_dword = 0;
>+	u32 i = 0;
> 
> 	/* Apply masks to input data */
>-	input->dword_stream[0]  &= input_mask->dword_stream[0];
>-	input->dword_stream[1]  &= input_mask->dword_stream[1];
>-	input->dword_stream[2]  &= input_mask->dword_stream[2];
>-	input->dword_stream[3]  &= input_mask->dword_stream[3];
>-	input->dword_stream[4]  &= input_mask->dword_stream[4];
>-	input->dword_stream[5]  &= input_mask->dword_stream[5];
>-	input->dword_stream[6]  &= input_mask->dword_stream[6];
>-	input->dword_stream[7]  &= input_mask->dword_stream[7];
>-	input->dword_stream[8]  &= input_mask->dword_stream[8];
>-	input->dword_stream[9]  &= input_mask->dword_stream[9];
>-	input->dword_stream[10] &= input_mask->dword_stream[10];
>+	for (i = 0; i < 14; i++)
>+		input->dword_stream[i]  &= input_mask->dword_stream[i];
> 
> 	/* record the flow_vm_vlan bits as they are a key part to the hash */
> 	flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
> 
> 	/* generate common hash dword */
>-	hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
>-				    input->dword_stream[2] ^
>-				    input->dword_stream[3] ^
>-				    input->dword_stream[4] ^
>-				    input->dword_stream[5] ^
>-				    input->dword_stream[6] ^
>-				    input->dword_stream[7] ^
>-				    input->dword_stream[8] ^
>-				    input->dword_stream[9] ^
>-				    input->dword_stream[10]);
>+	for (i = 1; i <= 13; i++)
>+		hi_dword ^= input->dword_stream[i];
>+	hi_hash_dword = IXGBE_NTOHL(hi_dword);
> 
> 	/* low dword is word swapped version of common */
> 	lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
>@@ -1734,26 +1808,13 @@
> 	/*
> 	 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
> 	 * delay this because bit 0 of the stream should not be processed
>-	 * so we do not add the vlan until after bit 0 was processed
>+	 * so we do not add the VLAN until after bit 0 was processed
> 	 */
> 	lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
> 
> 	/* Process remaining 30 bit of the key */
>-	IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
>-	IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
>-	IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
>-	IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
>-	IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
>-	IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
>-	IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
>-	IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
>-	IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
>-	IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
>-	IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
>-	IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
>-	IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
>-	IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
>-	IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
>+	for (i = 1; i <= 15; i++)
>+		IXGBE_COMPUTE_BKT_HASH_ITERATION(i);
> 
> 	/*
> 	 * Limit hash to 13 bits since max bucket count is 8K.
>@@ -1763,7 +1824,7 @@
> }
> 
> /**
>- *  ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
>+ *  ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks
>  *  @input_mask: mask to be bit swapped
>  *
>  *  The source and destination port masks for flow director are bit swapped
>@@ -1800,12 +1861,12 @@
> 	IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
> 
> s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
>-				    union ixgbe_atr_input *input_mask)
>+				    union ixgbe_atr_input *input_mask, bool cloud_mode)
> {
> 	/* mask IPv6 since it is currently not supported */
> 	u32 fdirm = IXGBE_FDIRM_DIPv6;
> 	u32 fdirtcpm;
>-
>+	UNREFERENCED_1PARAMETER(cloud_mode);
> 	DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
> 
> 	/*
>@@ -1878,59 +1939,69 @@
> 		return IXGBE_ERR_CONFIG;
> 	}
> 
>+
> 	/* Now mask VM pool and destination IPv6 - bits 5 and 2 */
> 	IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
> 
>-	/* store the TCP/UDP port masks, bit reversed from port layout */
>-	fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
>+	if (!cloud_mode) {
>+		/* store the TCP/UDP port masks, bit reversed from port
>+		 * layout */
>+		fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
> 
>-	/* write both the same so that UDP and TCP use the same mask */
>-	IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
>-	IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
>+		/* write both the same so that UDP and TCP use the same mask */
>+		IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
>+		IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
> 
>-	/* store source and destination IP masks (big-enian) */
>-	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
>-			     ~input_mask->formatted.src_ip[0]);
>-	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
>-			     ~input_mask->formatted.dst_ip[0]);
>-
>+		/* store source and destination IP masks (big-enian) */
>+		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
>+				     ~input_mask->formatted.src_ip[0]);
>+		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
>+				     ~input_mask->formatted.dst_ip[0]);
>+	}
> 	return IXGBE_SUCCESS;
> }
> 
> s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
> 					  union ixgbe_atr_input *input,
>-					  u16 soft_id, u8 queue)
>+					  u16 soft_id, u8 queue, bool cloud_mode)
> {
> 	u32 fdirport, fdirvlan, fdirhash, fdircmd;
>+	s32 err;
>+	UNREFERENCED_1PARAMETER(cloud_mode);
> 
> 	DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
>+	if (!cloud_mode) {
>+		/* currently IPv6 is not supported, must be programmed with 0 */
>+		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
>+				     input->formatted.src_ip[0]);
>+		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
>+				     input->formatted.src_ip[1]);
>+		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
>+				     input->formatted.src_ip[2]);
> 
>-	/* currently IPv6 is not supported, must be programmed with 0 */
>-	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
>-			     input->formatted.src_ip[0]);
>-	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
>-			     input->formatted.src_ip[1]);
>-	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
>-			     input->formatted.src_ip[2]);
>+		/* record the source address (big-endian) */
>+		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA,
>+			input->formatted.src_ip[0]);
> 
>-	/* record the source address (big-endian) */
>-	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
>+		/* record the first 32 bits of the destination address
>+		 * (big-endian) */
>+		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA,
>+			input->formatted.dst_ip[0]);
> 
>-	/* record the first 32 bits of the destination address (big-endian) */
>-	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
>+		/* record source and destination port (little-endian)*/
>+		fdirport = IXGBE_NTOHS(input->formatted.dst_port);
>+		fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
>+		fdirport |= IXGBE_NTOHS(input->formatted.src_port);
>+		IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
>+	}
> 
>-	/* record source and destination port (little-endian)*/
>-	fdirport = IXGBE_NTOHS(input->formatted.dst_port);
>-	fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
>-	fdirport |= IXGBE_NTOHS(input->formatted.src_port);
>-	IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
>-
>-	/* record vlan (little-endian) and flex_bytes(big-endian) */
>+	/* record VLAN (little-endian) and flex_bytes(big-endian) */
> 	fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
> 	fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
> 	fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
> 	IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
> 
>+
> 	/* configure FDIRHASH register */
> 	fdirhash = input->formatted.bkt_hash;
> 	fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
>@@ -1947,11 +2018,18 @@
> 		  IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
> 	if (queue == IXGBE_FDIR_DROP_QUEUE)
> 		fdircmd |= IXGBE_FDIRCMD_DROP;
>+	if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK)
>+		fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
> 	fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
> 	fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
> 	fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
> 
> 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
>+	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
>+	if (err) {
>+		DEBUGOUT("Flow Director command did not complete!\n");
>+		return err;
>+	}
> 
> 	return IXGBE_SUCCESS;
> }
>@@ -1961,9 +2039,8 @@
> 					  u16 soft_id)
> {
> 	u32 fdirhash;
>-	u32 fdircmd = 0;
>-	u32 retry_count;
>-	s32 err = IXGBE_SUCCESS;
>+	u32 fdircmd;
>+	s32 err;
> 
> 	/* configure FDIRHASH register */
> 	fdirhash = input->formatted.bkt_hash;
>@@ -1976,18 +2053,12 @@
> 	/* Query if filter is present */
> 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
> 
>-	for (retry_count = 10; retry_count; retry_count--) {
>-		/* allow 10us for query to process */
>-		usec_delay(10);
>-		/* verify query completed successfully */
>-		fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
>-		if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
>-			break;
>+	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
>+	if (err) {
>+		DEBUGOUT("Flow Director command did not complete!\n");
>+		return err;
> 	}
> 
>-	if (!retry_count)
>-		err = IXGBE_ERR_FDIR_REINIT_FAILED;
>-
> 	/* if filter exists in hardware then remove it */
> 	if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
> 		IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
>@@ -1996,7 +2067,7 @@
> 				IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
> 	}
> 
>-	return err;
>+	return IXGBE_SUCCESS;
> }
> 
> /**
>@@ -2013,9 +2084,10 @@
> s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
> 					union ixgbe_atr_input *input,
> 					union ixgbe_atr_input *input_mask,
>-					u16 soft_id, u8 queue)
>+					u16 soft_id, u8 queue, bool cloud_mode)
> {
> 	s32 err = IXGBE_ERR_CONFIG;
>+	UNREFERENCED_1PARAMETER(cloud_mode);
> 
> 	DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
> 
>@@ -2025,6 +2097,7 @@
> 	 */
> 	switch (input->formatted.flow_type) {
> 	case IXGBE_ATR_FLOW_TYPE_IPV4:
>+	case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4:
> 		input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
> 		if (input->formatted.dst_port || input->formatted.src_port) {
> 			DEBUGOUT(" Error on src/dst port\n");
>@@ -2032,12 +2105,15 @@
> 		}
> 		break;
> 	case IXGBE_ATR_FLOW_TYPE_SCTPV4:
>+	case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4:
> 		if (input->formatted.dst_port || input->formatted.src_port) {
> 			DEBUGOUT(" Error on src/dst port\n");
> 			return IXGBE_ERR_CONFIG;
> 		}
> 	case IXGBE_ATR_FLOW_TYPE_TCPV4:
>+	case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4:
> 	case IXGBE_ATR_FLOW_TYPE_UDPV4:
>+	case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4:
> 		input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
> 						  IXGBE_ATR_L4TYPE_MASK;
> 		break;
>@@ -2047,7 +2123,7 @@
> 	}
> 
> 	/* program input mask into the HW */
>-	err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
>+	err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode);
> 	if (err)
> 		return err;
> 
>@@ -2056,7 +2132,7 @@
> 
> 	/* program filters to filter memory */
> 	return ixgbe_fdir_write_perfect_filter_82599(hw, input,
>-						     soft_id, queue);
>+						     soft_id, queue, cloud_mode);
> }
> 
> /**
>@@ -2146,7 +2222,7 @@
>  **/
> s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
> {
>-	s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
>+	s32 status;
> 
> 	DEBUGFUNC("ixgbe_identify_phy_82599");
> 
>@@ -2155,7 +2231,7 @@
> 	if (status != IXGBE_SUCCESS) {
> 		/* 82599 10GBASE-T requires an external PHY */
> 		if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
>-			goto out;
>+			return status;
> 		else
> 			status = ixgbe_identify_module_generic(hw);
> 	}
>@@ -2163,14 +2239,13 @@
> 	/* Set PHY type none if no PHY detected */
> 	if (hw->phy.type == ixgbe_phy_unknown) {
> 		hw->phy.type = ixgbe_phy_none;
>-		status = IXGBE_SUCCESS;
>+		return IXGBE_SUCCESS;
> 	}
> 
> 	/* Return error if SFP module has been detected but is not supported */
> 	if (hw->phy.type == ixgbe_phy_sfp_unsupported)
>-		status = IXGBE_ERR_SFP_NOT_SUPPORTED;
>+		return IXGBE_ERR_SFP_NOT_SUPPORTED;
> 
>-out:
> 	return status;
> }
> 
>@@ -2189,8 +2264,6 @@
> 	u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
> 	u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
> 	u16 ext_ability = 0;
>-	u8 comp_codes_10g = 0;
>-	u8 comp_codes_1g = 0;
> 
> 	DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
> 
>@@ -2258,40 +2331,7 @@
> 	/* SFP check must be done last since DA modules are sometimes used to
> 	 * test KR mode -  we need to id KR mode correctly before SFP module.
> 	 * Call identify_sfp because the pluggable module may have changed */
>-	hw->phy.ops.identify_sfp(hw);
>-	if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
>-		goto out;
>-
>-	switch (hw->phy.type) {
>-	case ixgbe_phy_sfp_passive_tyco:
>-	case ixgbe_phy_sfp_passive_unknown:
>-		physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
>-		break;
>-	case ixgbe_phy_sfp_ftl_active:
>-	case ixgbe_phy_sfp_active_unknown:
>-		physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
>-		break;
>-	case ixgbe_phy_sfp_avago:
>-	case ixgbe_phy_sfp_ftl:
>-	case ixgbe_phy_sfp_intel:
>-	case ixgbe_phy_sfp_unknown:
>-		hw->phy.ops.read_i2c_eeprom(hw,
>-		      IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
>-		hw->phy.ops.read_i2c_eeprom(hw,
>-		      IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
>-		if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
>-			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
>-		else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
>-			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
>-		else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
>-			physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
>-		else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
>-			physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
>-		break;
>-	default:
>-		break;
>-	}
>-
>+	physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
> out:
> 	return physical_layer;
> }
>@@ -2317,7 +2357,10 @@
> 
> 	hw->mac.ops.disable_sec_rx_path(hw);
> 
>-	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
>+	if (regval & IXGBE_RXCTRL_RXEN)
>+		ixgbe_enable_rx(hw);
>+	else
>+		ixgbe_disable_rx(hw);
> 
> 	hw->mac.ops.enable_sec_rx_path(hw);
> 
>@@ -2325,7 +2368,7 @@
> }
> 
> /**
>- *  ixgbe_verify_fw_version_82599 - verify fw version for 82599
>+ *  ixgbe_verify_fw_version_82599 - verify FW version for 82599
>  *  @hw: pointer to hardware structure
>  *
>  *  Verifies that installed the firmware version is 0.6 or higher
>@@ -2419,7 +2462,7 @@
> 	    (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
> 		goto out;
> 
>-	/* get the lesm state word */
>+	/* get the LESM state word */
> 	status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
> 				     IXGBE_FW_LESM_STATE_1),
> 				     &fw_lesm_state);
>@@ -2504,7 +2547,7 @@
>  *  @hw: pointer to hardware structure
>  *
>  * Reset pipeline by asserting Restart_AN together with LMS change to ensure
>- * full pipeline reset
>+ * full pipeline reset.  This function assumes the SW/FW lock is held.
>  **/
> s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
> {
>@@ -2520,10 +2563,11 @@
> 		IXGBE_WRITE_FLUSH(hw);
> 	}
> 
>-	autoc_reg = hw->mac.cached_autoc;
>+	autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
> 	autoc_reg |= IXGBE_AUTOC_AN_RESTART;
> 	/* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
>-	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN);
>+	IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
>+			autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT));
> 	/* Wait for AN to leave state 0 */
> 	for (i = 0; i < 10; i++) {
> 		msec_delay(4);
>@@ -2549,4 +2593,117 @@
> }
> 
> 
>+/**
>+ *  ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
>+ *  @hw: pointer to hardware structure
>+ *  @byte_offset: byte offset to read
>+ *  @data: value read
>+ *
>+ *  Performs byte read operation to SFP module's EEPROM over I2C interface at
>+ *  a specified device address.
>+ **/
>+static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
>+				u8 dev_addr, u8 *data)
>+{
>+	u32 esdp;
>+	s32 status;
>+	s32 timeout = 200;
> 
>+	DEBUGFUNC("ixgbe_read_i2c_byte_82599");
>+
>+	if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
>+		/* Acquire I2C bus ownership. */
>+		esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
>+		esdp |= IXGBE_ESDP_SDP0;
>+		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
>+		IXGBE_WRITE_FLUSH(hw);
>+
>+		while (timeout) {
>+			esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
>+			if (esdp & IXGBE_ESDP_SDP1)
>+				break;
>+
>+			msec_delay(5);
>+			timeout--;
>+		}
>+
>+		if (!timeout) {
>+			DEBUGOUT("Driver can't access resource,"
>+				 " acquiring I2C bus timeout.\n");
>+			status = IXGBE_ERR_I2C;
>+			goto release_i2c_access;
>+		}
>+	}
>+
>+	status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
>+
>+release_i2c_access:
>+
>+	if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
>+		/* Release I2C bus ownership. */
>+		esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
>+		esdp &= ~IXGBE_ESDP_SDP0;
>+		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
>+		IXGBE_WRITE_FLUSH(hw);
>+	}
>+
>+	return status;
>+}
>+
>+/**
>+ *  ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
>+ *  @hw: pointer to hardware structure
>+ *  @byte_offset: byte offset to write
>+ *  @data: value to write
>+ *
>+ *  Performs byte write operation to SFP module's EEPROM over I2C interface at
>+ *  a specified device address.
>+ **/
>+static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
>+				 u8 dev_addr, u8 data)
>+{
>+	u32 esdp;
>+	s32 status;
>+	s32 timeout = 200;
>+
>+	DEBUGFUNC("ixgbe_write_i2c_byte_82599");
>+
>+	if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
>+		/* Acquire I2C bus ownership. */
>+		esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
>+		esdp |= IXGBE_ESDP_SDP0;
>+		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
>+		IXGBE_WRITE_FLUSH(hw);
>+
>+		while (timeout) {
>+			esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
>+			if (esdp & IXGBE_ESDP_SDP1)
>+				break;
>+
>+			msec_delay(5);
>+			timeout--;
>+		}
>+
>+		if (!timeout) {
>+			DEBUGOUT("Driver can't access resource,"
>+				 " acquiring I2C bus timeout.\n");
>+			status = IXGBE_ERR_I2C;
>+			goto release_i2c_access;
>+		}
>+	}
>+
>+	status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
>+
>+release_i2c_access:
>+
>+	if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
>+		/* Release I2C bus ownership. */
>+		esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
>+		esdp &= ~IXGBE_ESDP_SDP0;
>+		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
>+		IXGBE_WRITE_FLUSH(hw);
>+	}
>+
>+	return status;
>+}
>+
>Index: ixgbe_82599.h
>===================================================================
>--- ixgbe_82599.h	(revision 273551)
>+++ ixgbe_82599.h	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>@@ -61,4 +61,6 @@
> s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw);
> u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
> s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);
>+s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val);
>+s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 reg_val, bool locked);
> #endif /* _IXGBE_82599_H_ */
>Index: ixgbe_api.c
>===================================================================
>--- ixgbe_api.c	(revision 273551)
>+++ ixgbe_api.c	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>@@ -78,13 +78,13 @@
> 	case ixgbe_mac_82599EB:
> 		status = ixgbe_init_ops_82599(hw);
> 		break;
>+	case ixgbe_mac_X540:
>+		status = ixgbe_init_ops_X540(hw);
>+		break;
> 	case ixgbe_mac_82599_vf:
> 	case ixgbe_mac_X540_vf:
> 		status = ixgbe_init_ops_vf(hw);
> 		break;
>-	case ixgbe_mac_X540:
>-		status = ixgbe_init_ops_X540(hw);
>-		break;
> 	default:
> 		status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
> 		break;
>@@ -138,6 +138,7 @@
> 	case IXGBE_DEV_ID_82599_SFP_EM:
> 	case IXGBE_DEV_ID_82599_SFP_SF2:
> 	case IXGBE_DEV_ID_82599_SFP_SF_QP:
>+	case IXGBE_DEV_ID_82599_QSFP_SF_QP:
> 	case IXGBE_DEV_ID_82599EN_SFP:
> 	case IXGBE_DEV_ID_82599_CX4:
> 	case IXGBE_DEV_ID_82599_BYPASS:
>@@ -153,6 +154,7 @@
> 		hw->mac.type = ixgbe_mac_X540_vf;
> 		break;
> 	case IXGBE_DEV_ID_X540T:
>+	case IXGBE_DEV_ID_X540T1:
> 	case IXGBE_DEV_ID_X540_BYPASS:
> 		hw->mac.type = ixgbe_mac_X540;
> 		break;
>@@ -512,6 +514,20 @@
> }
> 
> /**
>+ * ixgbe_setup_internal_phy - Configure integrated PHY
>+ * @hw: pointer to hardware structure
>+ *
>+ * Reconfigure the integrated PHY in order to enable talk to the external PHY.
>+ * Returns success if not implemented, since nothing needs to be done in this
>+ * case.
>+ */
>+s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw)
>+{
>+	return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw),
>+			       IXGBE_SUCCESS);
>+}
>+
>+/**
>  *  ixgbe_check_phy_link - Determine link and speed status
>  *  @hw: pointer to hardware structure
>  *
>@@ -1064,6 +1080,7 @@
>  *  ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address
>  *  @hw: pointer to hardware structure
>  *  @byte_offset: byte offset to read
>+ *  @dev_addr: I2C bus address to read from
>  *  @data: value read
>  *
>  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
>@@ -1076,9 +1093,25 @@
> }
> 
> /**
>+ * ixgbe_read_i2c_combined - Perform I2C read combined operation
>+ * @hw: pointer to the hardware structure
>+ * @addr: I2C bus address to read from
>+ * @reg: I2C device register to read from
>+ * @val: pointer to location to receive read value
>+ *
>+ * Returns an error code on error.
>+ */
>+s32 ixgbe_read_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)
>+{
>+	return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined, (hw, addr,
>+			       reg, val), IXGBE_NOT_IMPLEMENTED);
>+}
>+
>+/**
>  *  ixgbe_write_i2c_byte - Writes 8 bit word over I2C
>  *  @hw: pointer to hardware structure
>  *  @byte_offset: byte offset to write
>+ *  @dev_addr: I2C bus address to write to
>  *  @data: value to write
>  *
>  *  Performs byte write operation to SFP module's EEPROM over I2C interface
>@@ -1092,6 +1125,21 @@
> }
> 
> /**
>+ * ixgbe_write_i2c_combined - Perform I2C write combined operation
>+ * @hw: pointer to the hardware structure
>+ * @addr: I2C bus address to write to
>+ * @reg: I2C device register to write to
>+ * @val: value to write
>+ *
>+ * Returns an error code on error.
>+ */
>+s32 ixgbe_write_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)
>+{
>+	return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined, (hw, addr,
>+			       reg, val), IXGBE_NOT_IMPLEMENTED);
>+}
>+
>+/**
>  *  ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
>  *  @hw: pointer to hardware structure
>  *  @byte_offset: EEPROM byte offset to write
>@@ -1179,7 +1227,7 @@
>  *  Acquires the SWFW semaphore through SW_FW_SYNC register for the specified
>  *  function (CSR, PHY0, PHY1, EEPROM, Flash)
>  **/
>-s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
>+s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)
> {
> 	return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,
> 			       (hw, mask), IXGBE_NOT_IMPLEMENTED);
>@@ -1193,9 +1241,21 @@
>  *  Releases the SWFW semaphore through SW_FW_SYNC register for the specified
>  *  function (CSR, PHY0, PHY1, EEPROM, Flash)
>  **/
>-void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
>+void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)
> {
> 	if (hw->mac.ops.release_swfw_sync)
> 		hw->mac.ops.release_swfw_sync(hw, mask);
> }
> 
>+
>+void ixgbe_disable_rx(struct ixgbe_hw *hw)
>+{
>+	if (hw->mac.ops.disable_rx)
>+		hw->mac.ops.disable_rx(hw);
>+}
>+
>+void ixgbe_enable_rx(struct ixgbe_hw *hw)
>+{
>+	if (hw->mac.ops.enable_rx)
>+		hw->mac.ops.enable_rx(hw);
>+}
>Index: ixgbe_api.h
>===================================================================
>--- ixgbe_api.h	(revision 273551)
>+++ ixgbe_api.h	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>@@ -69,6 +69,7 @@
> 			u16 phy_data);
> 
> s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw);
>+s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw);
> s32 ixgbe_check_phy_link(struct ixgbe_hw *hw,
> 			 ixgbe_link_speed *speed,
> 			 bool *link_up);
>@@ -139,16 +140,17 @@
> s32 ixgbe_mng_fw_enabled(struct ixgbe_hw *hw);
> s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
> s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
>-s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
>+s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
>+					bool cloud_mode);
> s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
> 					  union ixgbe_atr_hash_dword input,
> 					  union ixgbe_atr_hash_dword common,
> 					  u8 queue);
> s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
>-				    union ixgbe_atr_input *input_mask);
>+				    union ixgbe_atr_input *input_mask, bool cloud_mode);
> s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
> 					  union ixgbe_atr_input *input,
>-					  u16 soft_id, u8 queue);
>+					  u16 soft_id, u8 queue, bool cloud_mode);
> s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
> 					  union ixgbe_atr_input *input,
> 					  u16 soft_id);
>@@ -156,7 +158,8 @@
> 					union ixgbe_atr_input *input,
> 					union ixgbe_atr_input *mask,
> 					u16 soft_id,
>-					u8 queue);
>+					u8 queue,
>+					bool cloud_mode);
> void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
> 					  union ixgbe_atr_input *mask);
> u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
>@@ -164,16 +167,20 @@
> bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
> s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
> 			u8 *data);
>+s32 ixgbe_read_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val);
> s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
> 			 u8 data);
>+s32 ixgbe_write_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val);
> s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data);
> s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
> s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
> s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps);
>-s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
>-void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
>+s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask);
>+void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask);
> s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
> 			 u16 *wwpn_prefix);
> s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs);
>+void ixgbe_disable_rx(struct ixgbe_hw *hw);
>+void ixgbe_enable_rx(struct ixgbe_hw *hw);
> 
> #endif /* _IXGBE_API_H_ */
>Index: ixgbe_common.c
>===================================================================
>--- ixgbe_common.c	(revision 273551)
>+++ ixgbe_common.c	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>@@ -106,6 +106,8 @@
> 	mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
> 	mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
> 	mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
>+	mac->ops.prot_autoc_read = &prot_autoc_read_generic;
>+	mac->ops.prot_autoc_write = &prot_autoc_write_generic;
> 
> 	/* LEDs */
> 	mac->ops.led_on = &ixgbe_led_on_generic;
>@@ -128,6 +130,8 @@
> 	mac->ops.set_vfta = NULL;
> 	mac->ops.set_vlvf = NULL;
> 	mac->ops.init_uta_tables = NULL;
>+	mac->ops.enable_rx = &ixgbe_enable_rx_generic;
>+	mac->ops.disable_rx = &ixgbe_disable_rx_generic;
> 
> 	/* Flow Control */
> 	mac->ops.fc_enable = &ixgbe_fc_enable_generic;
>@@ -162,6 +166,7 @@
> 
> 	switch (hw->phy.media_type) {
> 	case ixgbe_media_type_fiber_fixed:
>+	case ixgbe_media_type_fiber_qsfp:
> 	case ixgbe_media_type_fiber:
> 		hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
> 		/* if link is down, assume supported */
>@@ -179,6 +184,7 @@
> 		switch (hw->device_id) {
> 		case IXGBE_DEV_ID_82599_T3_LOM:
> 		case IXGBE_DEV_ID_X540T:
>+		case IXGBE_DEV_ID_X540T1:
> 		case IXGBE_DEV_ID_X540_BYPASS:
> 			supported = TRUE;
> 			break;
>@@ -206,14 +212,11 @@
> 	s32 ret_val = IXGBE_SUCCESS;
> 	u32 reg = 0, reg_bp = 0;
> 	u16 reg_cu = 0;
>-	bool got_lock = FALSE;
>+	bool locked = FALSE;
> 
> 	DEBUGFUNC("ixgbe_setup_fc");
> 
>-	/*
>-	 * Validate the requested mode.  Strict IEEE mode does not allow
>-	 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
>-	 */
>+	/* Validate the requested mode */
> 	if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
> 		ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
> 			   "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
>@@ -234,11 +237,18 @@
> 	 * we link at 10G, the 1G advertisement is harmless and vice versa.
> 	 */
> 	switch (hw->phy.media_type) {
>+	case ixgbe_media_type_backplane:
>+		/* some MAC's need RMW protection on AUTOC */
>+		ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &reg_bp);
>+		if (ret_val != IXGBE_SUCCESS)
>+			goto out;
>+
>+		/* only backplane uses autoc so fall though */
> 	case ixgbe_media_type_fiber_fixed:
>+	case ixgbe_media_type_fiber_qsfp:
> 	case ixgbe_media_type_fiber:
>-	case ixgbe_media_type_backplane:
> 		reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
>-		reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
>+
> 		break;
> 	case ixgbe_media_type_copper:
> 		hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
>@@ -310,7 +320,7 @@
> 		break;
> 	}
> 
>-	if (hw->mac.type != ixgbe_mac_X540) {
>+	if (hw->mac.type < ixgbe_mac_X540) {
> 		/*
> 		 * Enable auto-negotiation between the MAC & PHY;
> 		 * the MAC will advertise clause 37 flow control.
>@@ -333,28 +343,9 @@
> 	 */
> 	if (hw->phy.media_type == ixgbe_media_type_backplane) {
> 		reg_bp |= IXGBE_AUTOC_AN_RESTART;
>-		/* Need the SW/FW semaphore around AUTOC writes if 82599 and
>-		 * LESM is on, likewise reset_pipeline requries the lock as
>-		 * it also writes AUTOC.
>-		 */
>-		if ((hw->mac.type == ixgbe_mac_82599EB) &&
>-		    ixgbe_verify_lesm_fw_enabled_82599(hw)) {
>-			ret_val = hw->mac.ops.acquire_swfw_sync(hw,
>-							IXGBE_GSSR_MAC_CSR_SM);
>-			if (ret_val != IXGBE_SUCCESS) {
>-				ret_val = IXGBE_ERR_SWFW_SYNC;
>-				goto out;
>-			}
>-			got_lock = TRUE;
>-		}
>-
>-		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
>-		if (hw->mac.type == ixgbe_mac_82599EB)
>-			ixgbe_reset_pipeline_82599(hw);
>-
>-		if (got_lock)
>-			hw->mac.ops.release_swfw_sync(hw,
>-						      IXGBE_GSSR_MAC_CSR_SM);
>+		ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
>+		if (ret_val)
>+			goto out;
> 	} else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
> 		    (ixgbe_device_supports_autoneg_fc(hw))) {
> 		hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
>@@ -361,7 +352,7 @@
> 				      IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
> 	}
> 
>-	DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
>+	DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
> out:
> 	return ret_val;
> }
>@@ -793,7 +784,7 @@
> 				return ret_val;
> 		} else {
> 			if (eeprom_buf_size > (u32)(pba->word[1] +
>-					      pba->pba_block[0])) {
>+					      pba_block_size)) {
> 				memcpy(pba->pba_block,
> 				       &eeprom_buf[pba->word[1]],
> 				       pba_block_size * sizeof(u16));
>@@ -965,7 +956,8 @@
> {
> 	struct ixgbe_mac_info *mac = &hw->mac;
> 
>-	hw->bus.type = ixgbe_bus_type_pci_express;
>+	if (hw->bus.type == ixgbe_bus_type_unknown)
>+		hw->bus.type = ixgbe_bus_type_pci_express;
> 
> 	switch (link_status & IXGBE_PCI_LINK_WIDTH) {
> 	case IXGBE_PCI_LINK_WIDTH_1:
>@@ -1071,7 +1063,7 @@
> 	hw->adapter_stopped = TRUE;
> 
> 	/* Disable the receive unit */
>-	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
>+	ixgbe_disable_rx(hw);
> 
> 	/* Clear interrupt mask to stop interrupts from being generated */
> 	IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
>@@ -2107,8 +2099,10 @@
> /**
>  *  ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
>  *  @hw: pointer to hardware structure
>+ *
>+ *  Returns a negative error code on error, or the 16-bit checksum
>  **/
>-u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
>+s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
> {
> 	u16 i;
> 	u16 j;
>@@ -2121,9 +2115,9 @@
> 
> 	/* Include 0x0-0x3F in the checksum */
> 	for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
>-		if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) {
>+		if (hw->eeprom.ops.read(hw, i, &word)) {
> 			DEBUGOUT("EEPROM read failed\n");
>-			break;
>+			return IXGBE_ERR_EEPROM;
> 		}
> 		checksum += word;
> 	}
>@@ -2130,24 +2124,35 @@
> 
> 	/* Include all data from pointers except for the fw pointer */
> 	for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
>-		hw->eeprom.ops.read(hw, i, &pointer);
>+		if (hw->eeprom.ops.read(hw, i, &pointer)) {
>+			DEBUGOUT("EEPROM read failed\n");
>+			return IXGBE_ERR_EEPROM;
>+		}
> 
>-		/* Make sure the pointer seems valid */
>-		if (pointer != 0xFFFF && pointer != 0) {
>-			hw->eeprom.ops.read(hw, pointer, &length);
>+		/* If the pointer seems invalid */
>+		if (pointer == 0xFFFF || pointer == 0)
>+			continue;
> 
>-			if (length != 0xFFFF && length != 0) {
>-				for (j = pointer+1; j <= pointer+length; j++) {
>-					hw->eeprom.ops.read(hw, j, &word);
>-					checksum += word;
>-				}
>+		if (hw->eeprom.ops.read(hw, pointer, &length)) {
>+			DEBUGOUT("EEPROM read failed\n");
>+			return IXGBE_ERR_EEPROM;
>+		}
>+
>+		if (length == 0xFFFF || length == 0)
>+			continue;
>+
>+		for (j = pointer + 1; j <= pointer + length; j++) {
>+			if (hw->eeprom.ops.read(hw, j, &word)) {
>+				DEBUGOUT("EEPROM read failed\n");
>+				return IXGBE_ERR_EEPROM;
> 			}
>+			checksum += word;
> 		}
> 	}
> 
> 	checksum = (u16)IXGBE_EEPROM_SUM - checksum;
> 
>-	return checksum;
>+	return (s32)checksum;
> }
> 
> /**
>@@ -2167,32 +2172,38 @@
> 
> 	DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
> 
>-	/*
>-	 * Read the first word from the EEPROM. If this times out or fails, do
>+	/* Read the first word from the EEPROM. If this times out or fails, do
> 	 * not continue or we could be in for a very long wait while every
> 	 * EEPROM read fails
> 	 */
> 	status = hw->eeprom.ops.read(hw, 0, &checksum);
>+	if (status) {
>+		DEBUGOUT("EEPROM read failed\n");
>+		return status;
>+	}
> 
>-	if (status == IXGBE_SUCCESS) {
>-		checksum = hw->eeprom.ops.calc_checksum(hw);
>+	status = hw->eeprom.ops.calc_checksum(hw);
>+	if (status < 0)
>+		return status;
> 
>-		hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
>+	checksum = (u16)(status & 0xffff);
> 
>-		/*
>-		 * Verify read checksum from EEPROM is the same as
>-		 * calculated checksum
>-		 */
>-		if (read_checksum != checksum)
>-			status = IXGBE_ERR_EEPROM_CHECKSUM;
>-
>-		/* If the user cares, return the calculated checksum */
>-		if (checksum_val)
>-			*checksum_val = checksum;
>-	} else {
>+	status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
>+	if (status) {
> 		DEBUGOUT("EEPROM read failed\n");
>+		return status;
> 	}
> 
>+	/* Verify read checksum from EEPROM is the same as
>+	 * calculated checksum
>+	 */
>+	if (read_checksum != checksum)
>+		status = IXGBE_ERR_EEPROM_CHECKSUM;
>+
>+	/* If the user cares, return the calculated checksum */
>+	if (checksum_val)
>+		*checksum_val = checksum;
>+
> 	return status;
> }
> 
>@@ -2207,21 +2218,24 @@
> 
> 	DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
> 
>-	/*
>-	 * Read the first word from the EEPROM. If this times out or fails, do
>+	/* Read the first word from the EEPROM. If this times out or fails, do
> 	 * not continue or we could be in for a very long wait while every
> 	 * EEPROM read fails
> 	 */
> 	status = hw->eeprom.ops.read(hw, 0, &checksum);
>-
>-	if (status == IXGBE_SUCCESS) {
>-		checksum = hw->eeprom.ops.calc_checksum(hw);
>-		status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
>-					      checksum);
>-	} else {
>+	if (status) {
> 		DEBUGOUT("EEPROM read failed\n");
>+		return status;
> 	}
> 
>+	status = hw->eeprom.ops.calc_checksum(hw);
>+	if (status < 0)
>+		return status;
>+
>+	checksum = (u16)(status & 0xffff);
>+
>+	status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
>+
> 	return status;
> }
> 
>@@ -2793,10 +2807,11 @@
> 			/*
> 			 * In order to prevent Tx hangs when the internal Tx
> 			 * switch is enabled we must set the high water mark
>-			 * to the maximum FCRTH value.  This allows the Tx
>-			 * switch to function even under heavy Rx workloads.
>+			 * to the Rx packet buffer size - 24KB.  This allows
>+			 * the Tx switch to function even under heavy Rx
>+			 * workloads.
> 			 */
>-			fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
>+			fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
> 		}
> 
> 		IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
>@@ -2888,8 +2903,7 @@
> 	linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
> 	if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
> 	    (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
>-		ERROR_REPORT1(IXGBE_ERROR_POLLING,
>-			     "Auto-Negotiation did not complete or timed out");
>+		DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
> 		goto out;
> 	}
> 
>@@ -2924,8 +2938,7 @@
> 	 */
> 	links = IXGBE_READ_REG(hw, IXGBE_LINKS);
> 	if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
>-		ERROR_REPORT1(IXGBE_ERROR_POLLING,
>-			     "Auto-Negotiation did not complete");
>+		DEBUGOUT("Auto-Negotiation did not complete\n");
> 		goto out;
> 	}
> 
>@@ -2932,8 +2945,7 @@
> 	if (hw->mac.type == ixgbe_mac_82599EB) {
> 		links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
> 		if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
>-			ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
>-				     "Link partner is not AN enabled");
>+			DEBUGOUT("Link partner is not AN enabled\n");
> 			goto out;
> 		}
> 	}
>@@ -3012,6 +3024,7 @@
> 	switch (hw->phy.media_type) {
> 	/* Autoneg flow control on fiber adapters */
> 	case ixgbe_media_type_fiber_fixed:
>+	case ixgbe_media_type_fiber_qsfp:
> 	case ixgbe_media_type_fiber:
> 		if (speed == IXGBE_LINK_SPEED_1GB_FULL)
> 			ret_val = ixgbe_fc_autoneg_fiber(hw);
>@@ -3101,6 +3114,7 @@
> {
> 	s32 status = IXGBE_SUCCESS;
> 	u32 i, poll;
>+	u16 value;
> 
> 	DEBUGFUNC("ixgbe_disable_pcie_master");
> 
>@@ -3108,7 +3122,8 @@
> 	IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
> 
> 	/* Exit if master requests are blocked */
>-	if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
>+	if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
>+	    IXGBE_REMOVED(hw->hw_addr))
> 		goto out;
> 
> 	/* Poll for master request bit to clear */
>@@ -3136,9 +3151,11 @@
> 	poll = ixgbe_pcie_timeout_poll(hw);
> 	for (i = 0; i < poll; i++) {
> 		usec_delay(100);
>-		if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) &
>-		    IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
>+		value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
>+		if (IXGBE_REMOVED(hw->hw_addr))
> 			goto out;
>+		if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
>+			goto out;
> 	}
> 
> 	ERROR_REPORT1(IXGBE_ERROR_POLLING,
>@@ -3157,7 +3174,7 @@
>  *  Acquires the SWFW semaphore through the GSSR register for the specified
>  *  function (CSR, PHY0, PHY1, EEPROM, Flash)
>  **/
>-s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
>+s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
> {
> 	u32 gssr = 0;
> 	u32 swmask = mask;
>@@ -3204,7 +3221,7 @@
>  *  Releases the SWFW semaphore through the GSSR register for the specified
>  *  function (CSR, PHY0, PHY1, EEPROM, Flash)
>  **/
>-void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
>+void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
> {
> 	u32 gssr;
> 	u32 swmask = mask;
>@@ -3258,6 +3275,37 @@
> }
> 
> /**
>+ *  prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
>+ *  @hw: pointer to hardware structure
>+ *  @reg_val: Value we read from AUTOC
>+ *
>+ *  The default case requires no protection so just to the register read.
>+ */
>+s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
>+{
>+	*locked = FALSE;
>+	*reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
>+	return IXGBE_SUCCESS;
>+}
>+
>+/**
>+ * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
>+ * @hw: pointer to hardware structure
>+ * @reg_val: value to write to AUTOC
>+ * @locked: bool to indicate whether the SW/FW lock was already taken by
>+ *           previous read.
>+ *
>+ * The default case requires no protection so just to the register write.
>+ */
>+s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
>+{
>+	UNREFERENCED_1PARAMETER(locked);
>+
>+	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
>+	return IXGBE_SUCCESS;
>+}
>+
>+/**
>  *  ixgbe_enable_sec_rx_path_generic - Enables the receive data path
>  *  @hw: pointer to hardware structure
>  *
>@@ -3288,7 +3336,10 @@
> {
> 	DEBUGFUNC("ixgbe_enable_rx_dma_generic");
> 
>-	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
>+	if (regval & IXGBE_RXCTRL_RXEN)
>+		ixgbe_enable_rx(hw);
>+	else
>+		ixgbe_disable_rx(hw);
> 
> 	return IXGBE_SUCCESS;
> }
>@@ -3302,9 +3353,10 @@
> {
> 	ixgbe_link_speed speed = 0;
> 	bool link_up = 0;
>-	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
>+	u32 autoc_reg = 0;
> 	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
> 	s32 ret_val = IXGBE_SUCCESS;
>+	bool locked = FALSE;
> 
> 	DEBUGFUNC("ixgbe_blink_led_start_generic");
> 
>@@ -3315,29 +3367,18 @@
> 	hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
> 
> 	if (!link_up) {
>-		/* Need the SW/FW semaphore around AUTOC writes if 82599 and
>-		 * LESM is on.
>-		 */
>-		bool got_lock = FALSE;
>-		if ((hw->mac.type == ixgbe_mac_82599EB) &&
>-		    ixgbe_verify_lesm_fw_enabled_82599(hw)) {
>-			ret_val = hw->mac.ops.acquire_swfw_sync(hw,
>-							IXGBE_GSSR_MAC_CSR_SM);
>-			if (ret_val != IXGBE_SUCCESS) {
>-				ret_val = IXGBE_ERR_SWFW_SYNC;
>-				goto out;
>-			}
>-			got_lock = TRUE;
>-		}
>+		ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
>+		if (ret_val != IXGBE_SUCCESS)
>+			goto out;
> 
> 		autoc_reg |= IXGBE_AUTOC_AN_RESTART;
> 		autoc_reg |= IXGBE_AUTOC_FLU;
>-		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
>+
>+		ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
>+		if (ret_val != IXGBE_SUCCESS)
>+			goto out;
>+
> 		IXGBE_WRITE_FLUSH(hw);
>-
>-		if (got_lock)
>-			hw->mac.ops.release_swfw_sync(hw,
>-						      IXGBE_GSSR_MAC_CSR_SM);
> 		msec_delay(10);
> 	}
> 
>@@ -3357,37 +3398,24 @@
>  **/
> s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
> {
>-	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
>+	u32 autoc_reg = 0;
> 	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
> 	s32 ret_val = IXGBE_SUCCESS;
>-	bool got_lock = FALSE;
>+	bool locked = FALSE;
> 
> 	DEBUGFUNC("ixgbe_blink_led_stop_generic");
>-	/* Need the SW/FW semaphore around AUTOC writes if 82599 and
>-	 * LESM is on.
>-	 */
>-	if ((hw->mac.type == ixgbe_mac_82599EB) &&
>-	    ixgbe_verify_lesm_fw_enabled_82599(hw)) {
>-		ret_val = hw->mac.ops.acquire_swfw_sync(hw,
>-						IXGBE_GSSR_MAC_CSR_SM);
>-		if (ret_val != IXGBE_SUCCESS) {
>-			ret_val = IXGBE_ERR_SWFW_SYNC;
>-			goto out;
>-		}
>-		got_lock = TRUE;
>-	}
> 
>+	ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
>+	if (ret_val != IXGBE_SUCCESS)
>+		goto out;
> 
> 	autoc_reg &= ~IXGBE_AUTOC_FLU;
> 	autoc_reg |= IXGBE_AUTOC_AN_RESTART;
>-	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
> 
>-	if (hw->mac.type == ixgbe_mac_82599EB)
>-		ixgbe_reset_pipeline_82599(hw);
>+	ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
>+	if (ret_val != IXGBE_SUCCESS)
>+		goto out;
> 
>-	if (got_lock)
>-		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
>-
> 	led_reg &= ~IXGBE_LED_MODE_MASK(index);
> 	led_reg &= ~IXGBE_LED_BLINK(index);
> 	led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
>@@ -3550,6 +3578,8 @@
> 
> 	DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
> 	msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
>+	if (IXGBE_REMOVED(hw->hw_addr))
>+		msix_count = 0;
> 	msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
> 
> 	/* MSI-X count is zero-based in HW */
>@@ -3653,6 +3683,9 @@
> 	mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
> 	mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
> 
>+	if (IXGBE_REMOVED(hw->hw_addr))
>+		goto done;
>+
> 	if (!mpsar_lo && !mpsar_hi)
> 		goto done;
> 
>@@ -4048,17 +4081,19 @@
> 			*link_up = FALSE;
> 	}
> 
>-	if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
>-	    IXGBE_LINKS_SPEED_10G_82599)
>+	switch (links_reg & IXGBE_LINKS_SPEED_82599) {
>+	case IXGBE_LINKS_SPEED_10G_82599:
> 		*speed = IXGBE_LINK_SPEED_10GB_FULL;
>-	else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
>-		 IXGBE_LINKS_SPEED_1G_82599)
>+		break;
>+	case IXGBE_LINKS_SPEED_1G_82599:
> 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
>-	else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
>-		 IXGBE_LINKS_SPEED_100_82599)
>+		break;
>+	case IXGBE_LINKS_SPEED_100_82599:
> 		*speed = IXGBE_LINK_SPEED_100_FULL;
>-	else
>+		break;
>+	default:
> 		*speed = IXGBE_LINK_SPEED_UNKNOWN;
>+	}
> 
> 	return IXGBE_SUCCESS;
> }
>@@ -4216,7 +4251,7 @@
>  *  ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
>  *  @hw: pointer to hardware structure
>  *  @enable: enable or disable switch for VLAN anti-spoofing
>- *  @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
>+ *  @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
>  *
>  **/
> void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
>@@ -4305,46 +4340,86 @@
> }
> 
> /**
>+ *  ixgbe_get_hi_status - Get host interface command status
>+ *  @hw: pointer to the HW structure
>+ *  @return_code: reads and returns code
>+ *
>+ *  Check if command returned with success. On success return IXGBE_SUCCESS
>+ *  else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
>+ **/
>+s32 ixgbe_get_hi_status(struct ixgbe_hw *hw, u8 *ret_status)
>+{
>+	struct ixgbe_hic_hdr response;
>+	u32 *response_val = (u32 *)&response;
>+
>+	DEBUGFUNC("ixgbe_get_host_interface_status");
>+
>+	/* Read the command response */
>+	*response_val = IXGBE_CPU_TO_LE32(IXGBE_READ_REG(hw, IXGBE_FLEX_MNG));
>+
>+	if (ret_status)
>+		*ret_status = response.cmd_or_resp.ret_status;
>+
>+	if (response.cmd_or_resp.ret_status != FW_CEM_RESP_STATUS_SUCCESS) {
>+		DEBUGOUT1("Host interface error=%x.\n",
>+			  response.cmd_or_resp.ret_status);
>+		return IXGBE_ERR_HOST_INTERFACE_COMMAND;
>+	}
>+
>+	return IXGBE_SUCCESS;
>+}
>+
>+/**
>  *  ixgbe_host_interface_command - Issue command to manageability block
>  *  @hw: pointer to the HW structure
>  *  @buffer: contains the command to write and where the return status will
>  *   be placed
>  *  @length: length of buffer, must be multiple of 4 bytes
>+ *  @timeout: time in ms to wait for command completion
>+ *  @return_data: read and return data from the buffer (TRUE) or not (FALSE)
>+ *   Needed because FW structures are big endian and decoding of
>+ *   these fields can be 8 bit or 16 bit based on command. Decoding
>+ *   is not easily understood without making a table of commands.
>+ *   So we will leave this up to the caller to read back the data
>+ *   in these cases.
>  *
>  *  Communicates with the manageability block.  On success return IXGBE_SUCCESS
>  *  else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
>  **/
> s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
>-				 u32 length)
>+				 u32 length, u32 timeout, bool return_data)
> {
>-	u32 hicr, i, bi;
>+	u32 hicr, i, bi, fwsts;
> 	u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
>-	u8 buf_len, dword_len;
>+	u16 buf_len;
>+	u16 dword_len;
> 
>-	s32 ret_val = IXGBE_SUCCESS;
>-
> 	DEBUGFUNC("ixgbe_host_interface_command");
> 
>-	if (length == 0 || length & 0x3 ||
>-	    length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
>-		DEBUGOUT("Buffer length failure.\n");
>-		ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
>-		goto out;
>+	if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
>+		DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
>+		return IXGBE_ERR_HOST_INTERFACE_COMMAND;
> 	}
>+	/* Set bit 9 of FWSTS clearing FW reset indication */
>+	fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
>+	IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
> 
> 	/* Check that the host interface is enabled. */
> 	hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
> 	if ((hicr & IXGBE_HICR_EN) == 0) {
> 		DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
>-		ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
>-		goto out;
>+		return IXGBE_ERR_HOST_INTERFACE_COMMAND;
> 	}
> 
>-	/* Calculate length in DWORDs */
>+	/* Calculate length in DWORDs. We must be DWORD aligned */
>+	if ((length % (sizeof(u32))) != 0) {
>+		DEBUGOUT("Buffer length failure, not aligned to dword");
>+		return IXGBE_ERR_INVALID_ARGUMENT;
>+	}
>+
> 	dword_len = length >> 2;
> 
>-	/*
>-	 * The device driver writes the relevant command block
>+	/* The device driver writes the relevant command block
> 	 * into the ram area.
> 	 */
> 	for (i = 0; i < dword_len; i++)
>@@ -4354,7 +4429,7 @@
> 	/* Setting this bit tells the ARC that a new command is pending. */
> 	IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
> 
>-	for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
>+	for (i = 0; i < timeout; i++) {
> 		hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
> 		if (!(hicr & IXGBE_HICR_C))
> 			break;
>@@ -4361,14 +4436,17 @@
> 		msec_delay(1);
> 	}
> 
>-	/* Check command successful completion. */
>-	if (i == IXGBE_HI_COMMAND_TIMEOUT ||
>-	    (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
>-		DEBUGOUT("Command has failed with no status valid.\n");
>-		ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
>-		goto out;
>+	/* Check command completion */
>+	if ((timeout != 0 && i == timeout) ||
>+	    !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
>+		ERROR_REPORT1(IXGBE_ERROR_CAUTION,
>+			     "Command has failed with no status valid.\n");
>+		return IXGBE_ERR_HOST_INTERFACE_COMMAND;
> 	}
> 
>+	if (!return_data)
>+		return 0;
>+
> 	/* Calculate length in DWORDs */
> 	dword_len = hdr_size >> 2;
> 
>@@ -4381,25 +4459,23 @@
> 	/* If there is any thing in data position pull it in */
> 	buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
> 	if (buf_len == 0)
>-		goto out;
>+		return 0;
> 
>-	if (length < (buf_len + hdr_size)) {
>+	if (length < buf_len + hdr_size) {
> 		DEBUGOUT("Buffer not large enough for reply message.\n");
>-		ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
>-		goto out;
>+		return IXGBE_ERR_HOST_INTERFACE_COMMAND;
> 	}
> 
> 	/* Calculate length in DWORDs, add 3 for odd lengths */
> 	dword_len = (buf_len + 3) >> 2;
> 
>-	/* Pull in the rest of the buffer (bi is where we left off)*/
>+	/* Pull in the rest of the buffer (bi is where we left off) */
> 	for (; bi <= dword_len; bi++) {
> 		buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
> 		IXGBE_LE32_TO_CPUS(&buffer[bi]);
> 	}
> 
>-out:
>-	return ret_val;
>+	return 0;
> }
> 
> /**
>@@ -4446,7 +4522,9 @@
> 
> 	for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
> 		ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
>-						       sizeof(fw_cmd));
>+						       sizeof(fw_cmd),
>+						       IXGBE_HI_COMMAND_TIMEOUT,
>+						       TRUE);
> 		if (ret_val != IXGBE_SUCCESS)
> 			continue;
> 
>@@ -4533,7 +4611,8 @@
>  **/
> void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
> {
>-	u32 gcr_ext, hlreg0;
>+	u32 gcr_ext, hlreg0, i, poll;
>+	u16 value;
> 
> 	/*
> 	 * If double reset is not requested then all transactions should
>@@ -4550,6 +4629,25 @@
> 	hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
> 	IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
> 
>+	/* Wait for a last completion before clearing buffers */
>+	IXGBE_WRITE_FLUSH(hw);
>+	msec_delay(3);
>+
>+	/*
>+	 * Before proceeding, make sure that the PCIe block does not have
>+	 * transactions pending.
>+	 */
>+	poll = ixgbe_pcie_timeout_poll(hw);
>+	for (i = 0; i < poll; i++) {
>+		usec_delay(100);
>+		value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
>+		if (IXGBE_REMOVED(hw->hw_addr))
>+			goto out;
>+		if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
>+			goto out;
>+	}
>+
>+out:
> 	/* initiate cleaning flow for buffers in the PCIe transaction layer */
> 	gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
> 	IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
>@@ -4582,3 +4680,70 @@
> 			(reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
> 	return;
> }
>+
>+void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
>+{
>+	u32 pfdtxgswc;
>+	u32 rxctrl;
>+
>+	rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
>+	if (rxctrl & IXGBE_RXCTRL_RXEN) {
>+		if (hw->mac.type != ixgbe_mac_82598EB) {
>+			pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
>+			if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
>+				pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
>+				IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
>+				hw->mac.set_lben = TRUE;
>+			} else {
>+				hw->mac.set_lben = FALSE;
>+			}
>+		}
>+		rxctrl &= ~IXGBE_RXCTRL_RXEN;
>+		IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
>+	}
>+}
>+
>+void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
>+{
>+	u32 pfdtxgswc;
>+	u32 rxctrl;
>+
>+	rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
>+	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
>+
>+	if (hw->mac.type != ixgbe_mac_82598EB) {
>+		if (hw->mac.set_lben) {
>+			pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
>+			pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
>+			IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
>+			hw->mac.set_lben = FALSE;
>+		}
>+	}
>+}
>+
>+/**
>+ * ixgbe_mng_enabled - Is the manageability engine enabled?
>+ * @hw: pointer to hardware structure
>+ *
>+ * Returns TRUE if the manageability engine is enabled.
>+ **/
>+bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
>+{
>+	u32 fwsm, manc, factps;
>+
>+	fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
>+	if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
>+		return FALSE;
>+
>+	manc = IXGBE_READ_REG(hw, IXGBE_MANC);
>+	if (!(manc & IXGBE_MANC_RCV_TCO_EN))
>+		return FALSE;
>+
>+	if (hw->mac.type <= ixgbe_mac_X540) {
>+		factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
>+		if (factps & IXGBE_FACTPS_MNGCG)
>+			return FALSE;
>+	}
>+
>+	return TRUE;
>+}
>Index: ixgbe_common.h
>===================================================================
>--- ixgbe_common.h	(revision 273551)
>+++ ixgbe_common.h	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>@@ -41,6 +41,7 @@
> 		IXGBE_WRITE_REG(hw, reg, (u32) value); \
> 		IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32)); \
> 	} while (0)
>+#define IXGBE_REMOVED(a) (0)
> #if !defined(NO_READ_PBA_RAW) || !defined(NO_WRITE_PBA_RAW)
> struct ixgbe_pba {
> 	u16 word[2];
>@@ -89,7 +90,7 @@
> 				       u16 *data);
> s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
> 					      u16 words, u16 *data);
>-u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);
>+s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);
> s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
> 					   u16 *checksum_val);
> s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
>@@ -115,10 +116,13 @@
> void ixgbe_fc_autoneg(struct ixgbe_hw *hw);
> 
> s32 ixgbe_validate_mac_addr(u8 *mac_addr);
>-s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
>-void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask);
>+s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask);
>+void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask);
> s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
> 
>+s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val);
>+s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked);
>+
> s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);
> s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);
> 
>@@ -154,11 +158,16 @@
> s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
> 				 u8 build, u8 ver);
> u8 ixgbe_calculate_checksum(u8 *buffer, u32 length);
>+s32 ixgbe_get_hi_status(struct ixgbe_hw *hw, u8 *ret_status);
> s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
>-				 u32 length);
>+				 u32 length, u32 timeout, bool return_data);
>+
> void ixgbe_clear_tx_pending(struct ixgbe_hw *hw);
> 
> extern s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw);
> extern void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw);
>+bool ixgbe_mng_enabled(struct ixgbe_hw *hw);
> 
>+void ixgbe_disable_rx_generic(struct ixgbe_hw *hw);
>+void ixgbe_enable_rx_generic(struct ixgbe_hw *hw);
> #endif /* IXGBE_COMMON */
>Index: ixgbe_dcb.c
>===================================================================
>--- ixgbe_dcb.c	(revision 273551)
>+++ ixgbe_dcb.c	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>Index: ixgbe_dcb.h
>===================================================================
>--- ixgbe_dcb.h	(revision 273551)
>+++ ixgbe_dcb.h	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>@@ -35,7 +35,6 @@
> #ifndef _IXGBE_DCB_H_
> #define _IXGBE_DCB_H_
> 
>-
> #include "ixgbe_type.h"
> 
> /* DCB defines */
>Index: ixgbe_dcb_82598.c
>===================================================================
>--- ixgbe_dcb_82598.c	(revision 273551)
>+++ ixgbe_dcb_82598.c	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>@@ -347,6 +347,8 @@
> 			      u16 *refill, u16 *max, u8 *bwg_id,
> 			      u8 *tsa)
> {
>+	UNREFERENCED_1PARAMETER(link_speed);
>+
> 	ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
> 	ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,
> 					       tsa);
>Index: ixgbe_dcb_82598.h
>===================================================================
>--- ixgbe_dcb_82598.h	(revision 273551)
>+++ ixgbe_dcb_82598.h	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>Index: ixgbe_dcb_82599.c
>===================================================================
>--- ixgbe_dcb_82599.c	(revision 273551)
>+++ ixgbe_dcb_82599.c	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>@@ -329,7 +329,14 @@
> 			fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
> 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
> 		} else {
>-			reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
>+			/*
>+			 * In order to prevent Tx hangs when the internal Tx
>+			 * switch is enabled we must set the high water mark
>+			 * to the Rx packet buffer size - 24KB.  This allows
>+			 * the Tx switch to function even under heavy Rx
>+			 * workloads.
>+			 */
>+			reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
> 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
> 		}
> 
>@@ -573,6 +580,7 @@
> 			      u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa,
> 			      u8 *map)
> {
>+	UNREFERENCED_1PARAMETER(link_speed);
> 
> 	ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, tsa,
> 					  map);
>Index: ixgbe_dcb_82599.h
>===================================================================
>--- ixgbe_dcb_82599.h	(revision 273551)
>+++ ixgbe_dcb_82599.h	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>Index: ixgbe_mbx.c
>===================================================================
>--- ixgbe_mbx.c	(revision 273551)
>+++ ixgbe_mbx.c	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2012, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>@@ -77,10 +77,11 @@
> 
> 	DEBUGFUNC("ixgbe_write_mbx");
> 
>-	if (size > mbx->size)
>+	if (size > mbx->size) {
> 		ret_val = IXGBE_ERR_MBX;
>-
>-	else if (mbx->ops.write)
>+		ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
>+			     "Invalid mailbox message size %d", size);
>+	} else if (mbx->ops.write)
> 		ret_val = mbx->ops.write(hw, msg, size, mbx_id);
> 
> 	return ret_val;
>@@ -170,6 +171,10 @@
> 		usec_delay(mbx->usec_delay);
> 	}
> 
>+	if (countdown == 0)
>+		ERROR_REPORT2(IXGBE_ERROR_POLLING,
>+			   "Polling for VF%d mailbox message timedout", mbx_id);
>+
> out:
> 	return countdown ? IXGBE_SUCCESS : IXGBE_ERR_MBX;
> }
>@@ -198,6 +203,10 @@
> 		usec_delay(mbx->usec_delay);
> 	}
> 
>+	if (countdown == 0)
>+		ERROR_REPORT2(IXGBE_ERROR_POLLING,
>+			     "Polling for VF%d mailbox ack timedout", mbx_id);
>+
> out:
> 	return countdown ? IXGBE_SUCCESS : IXGBE_ERR_MBX;
> }
>@@ -633,7 +642,11 @@
> 	p2v_mailbox = IXGBE_READ_REG(hw, IXGBE_PFMAILBOX(vf_number));
> 	if (p2v_mailbox & IXGBE_PFMAILBOX_PFU)
> 		ret_val = IXGBE_SUCCESS;
>+	else
>+		ERROR_REPORT2(IXGBE_ERROR_POLLING,
>+			   "Failed to obtain mailbox lock for VF%d", vf_number);
> 
>+
> 	return ret_val;
> }
> 
>Index: ixgbe_mbx.h
>===================================================================
>--- ixgbe_mbx.h	(revision 273551)
>+++ ixgbe_mbx.h	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>Index: ixgbe_phy.c
>===================================================================
>--- ixgbe_phy.c	(revision 273551)
>+++ ixgbe_phy.c	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>@@ -46,7 +46,7 @@
> static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
> static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
> static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
>-static bool ixgbe_get_i2c_data(u32 *i2cctl);
>+static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
> static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
> 					  u8 *sff8472_data);
> 
>@@ -99,6 +99,13 @@
> 
> 	DEBUGFUNC("ixgbe_identify_phy_generic");
> 
>+	if (!hw->phy.phy_semaphore_mask) {
>+		if (hw->bus.lan_id)
>+			hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
>+		else
>+			hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
>+	}
>+
> 	if (hw->phy.type == ixgbe_phy_unknown) {
> 		for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
> 			if (ixgbe_validate_phy_addr(hw, phy_addr)) {
>@@ -126,11 +133,13 @@
> 				break;
> 			}
> 		}
>-		/* clear value if nothing found */
>+
>+		/* Certain media types do not have a phy so an address will not
>+		 * be found and the code will take this path.  Caller has to
>+		 * decide if it is an error or not.
>+		 */
> 		if (status != IXGBE_SUCCESS) {
> 			hw->phy.addr = 0;
>-			ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
>-				     "Could not identify valid PHY address");
> 		}
> 	} else {
> 		status = IXGBE_SUCCESS;
>@@ -140,6 +149,35 @@
> }
> 
> /**
>+ * ixgbe_check_reset_blocked - check status of MNG FW veto bit
>+ * @hw: pointer to the hardware structure
>+ *
>+ * This function checks the MMNGC.MNG_VETO bit to see if there are
>+ * any constraints on link from manageability.  For MAC's that don't
>+ * have this bit just return faluse since the link can not be blocked
>+ * via this method.
>+ **/
>+s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
>+{
>+	u32 mmngc;
>+
>+	DEBUGFUNC("ixgbe_check_reset_blocked");
>+
>+	/* If we don't have this bit, it can't be blocking */
>+	if (hw->mac.type == ixgbe_mac_82598EB)
>+		return FALSE;
>+
>+	mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
>+	if (mmngc & IXGBE_MMNGC_MNG_VETO) {
>+		ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
>+			      "MNG_VETO bit detected.\n");
>+		return TRUE;
>+	}
>+
>+	return FALSE;
>+}
>+
>+/**
>  *  ixgbe_validate_phy_addr - Determines phy address is valid
>  *  @hw: pointer to hardware structure
>  *
>@@ -245,6 +283,10 @@
> 	    (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
> 		goto out;
> 
>+	/* Blocked by MNG FW so bail */
>+	if (ixgbe_check_reset_blocked(hw))
>+		goto out;
>+
> 	/*
> 	 * Perform soft PHY reset to the PHY_XS.
> 	 * This will cause a soft reset to the PHY
>@@ -368,15 +410,10 @@
> 			       u32 device_type, u16 *phy_data)
> {
> 	s32 status;
>-	u16 gssr;
>+	u32 gssr = hw->phy.phy_semaphore_mask;
> 
> 	DEBUGFUNC("ixgbe_read_phy_reg_generic");
> 
>-	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
>-		gssr = IXGBE_GSSR_PHY1_SM;
>-	else
>-		gssr = IXGBE_GSSR_PHY0_SM;
>-
> 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
> 		status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
> 						phy_data);
>@@ -474,15 +511,10 @@
> 				u32 device_type, u16 phy_data)
> {
> 	s32 status;
>-	u16 gssr;
>+	u32 gssr = hw->phy.phy_semaphore_mask;
> 
> 	DEBUGFUNC("ixgbe_write_phy_reg_generic");
> 
>-	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
>-		gssr = IXGBE_GSSR_PHY1_SM;
>-	else
>-		gssr = IXGBE_GSSR_PHY0_SM;
>-
> 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
> 		status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
> 						 phy_data);
>@@ -495,16 +527,14 @@
> }
> 
> /**
>- *  ixgbe_setup_phy_link_generic - Set and restart autoneg
>+ *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
>  *  @hw: pointer to hardware structure
>  *
>- *  Restart autonegotiation and PHY and waits for completion.
>+ *  Restart auto-negotiation and PHY and waits for completion.
>  **/
> s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
> {
> 	s32 status = IXGBE_SUCCESS;
>-	u32 time_out;
>-	u32 max_time_out = 10;
> 	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
> 	bool autoneg = FALSE;
> 	ixgbe_link_speed speed;
>@@ -561,7 +591,11 @@
> 				      autoneg_reg);
> 	}
> 
>-	/* Restart PHY autonegotiation and wait for completion */
>+	/* Blocked by MNG FW so don't reset PHY */
>+	if (ixgbe_check_reset_blocked(hw))
>+		return status;
>+
>+	/* Restart PHY auto-negotiation. */
> 	hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
> 			     IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
> 
>@@ -570,25 +604,6 @@
> 	hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
> 			      IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
> 
>-	/* Wait for autonegotiation to finish */
>-	for (time_out = 0; time_out < max_time_out; time_out++) {
>-		usec_delay(10);
>-		/* Restart PHY autonegotiation and wait for completion */
>-		status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
>-					      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
>-					      &autoneg_reg);
>-
>-		autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
>-		if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
>-			break;
>-	}
>-
>-	if (time_out == max_time_out) {
>-		status = IXGBE_ERR_LINK_SETUP;
>-		ERROR_REPORT1(IXGBE_ERROR_POLLING,
>-			     "PHY autonegotiation time out");
>-	}
>-
> 	return status;
> }
> 
>@@ -614,6 +629,12 @@
> 	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
> 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
> 
>+	if (speed & IXGBE_LINK_SPEED_5GB_FULL)
>+		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
>+
>+	if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
>+		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
>+
> 	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
> 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
> 
>@@ -632,13 +653,14 @@
>  *  @speed: pointer to link speed
>  *  @autoneg: boolean auto-negotiation value
>  *
>- *  Determines the link capabilities by reading the AUTOC register.
>+ *  Determines the supported link capabilities by reading the PHY auto
>+ *  negotiation register.
>  **/
> s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
> 					       ixgbe_link_speed *speed,
> 					       bool *autoneg)
> {
>-	s32 status = IXGBE_ERR_LINK_SETUP;
>+	s32 status;
> 	u16 speed_ability;
> 
> 	DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
>@@ -712,16 +734,14 @@
> }
> 
> /**
>- *	ixgbe_setup_phy_link_tnx - Set and restart autoneg
>+ *	ixgbe_setup_phy_link_tnx - Set and restart auto-neg
>  *	@hw: pointer to hardware structure
>  *
>- *	Restart autonegotiation and PHY and waits for completion.
>+ *	Restart auto-negotiation and PHY and waits for completion.
>  **/
> s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
> {
> 	s32 status = IXGBE_SUCCESS;
>-	u32 time_out;
>-	u32 max_time_out = 10;
> 	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
> 	bool autoneg = FALSE;
> 	ixgbe_link_speed speed;
>@@ -775,7 +795,11 @@
> 				      autoneg_reg);
> 	}
> 
>-	/* Restart PHY autonegotiation and wait for completion */
>+	/* Blocked by MNG FW so don't reset PHY */
>+	if (ixgbe_check_reset_blocked(hw))
>+		return status;
>+
>+	/* Restart PHY auto-negotiation. */
> 	hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
> 			     IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
> 
>@@ -784,24 +808,6 @@
> 	hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
> 			      IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
> 
>-	/* Wait for autonegotiation to finish */
>-	for (time_out = 0; time_out < max_time_out; time_out++) {
>-		usec_delay(10);
>-		/* Restart PHY autonegotiation and wait for completion */
>-		status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
>-					      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
>-					      &autoneg_reg);
>-
>-		autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
>-		if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
>-			break;
>-	}
>-
>-	if (time_out == max_time_out) {
>-		status = IXGBE_ERR_LINK_SETUP;
>-		DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
>-	}
>-
> 	return status;
> }
> 
>@@ -813,7 +819,7 @@
> s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
> 				       u16 *firmware_version)
> {
>-	s32 status = IXGBE_SUCCESS;
>+	s32 status;
> 
> 	DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
> 
>@@ -832,7 +838,7 @@
> s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
> 					   u16 *firmware_version)
> {
>-	s32 status = IXGBE_SUCCESS;
>+	s32 status;
> 
> 	DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
> 
>@@ -858,6 +864,10 @@
> 
> 	DEBUGFUNC("ixgbe_reset_phy_nl");
> 
>+	/* Blocked by MNG FW so bail */
>+	if (ixgbe_check_reset_blocked(hw))
>+		goto out;
>+
> 	hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
> 			     IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
> 
>@@ -972,6 +982,9 @@
> 		status = ixgbe_identify_sfp_module_generic(hw);
> 		break;
> 
>+	case ixgbe_media_type_fiber_qsfp:
>+		status = ixgbe_identify_qsfp_module_generic(hw);
>+		break;
> 
> 	default:
> 		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
>@@ -1068,7 +1081,7 @@
> 				hw->phy.sfp_type = ixgbe_sfp_type_lr;
> 			else
> 				hw->phy.sfp_type = ixgbe_sfp_type_unknown;
>-		} else if (hw->mac.type == ixgbe_mac_82599EB) {
>+		} else {
> 			if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
> 				if (hw->bus.lan_id == 0)
> 					hw->phy.sfp_type =
>@@ -1261,9 +1274,269 @@
> 	return IXGBE_ERR_SFP_NOT_PRESENT;
> }
> 
>+/**
>+ *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
>+ *  @hw: pointer to hardware structure
>+ *
>+ *  Determines physical layer capabilities of the current SFP.
>+ */
>+s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
>+{
>+	u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
>+	u8 comp_codes_10g = 0;
>+	u8 comp_codes_1g = 0;
> 
>+	DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
> 
>+	hw->phy.ops.identify_sfp(hw);
>+	if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
>+		return physical_layer;
>+
>+	switch (hw->phy.type) {
>+	case ixgbe_phy_sfp_passive_tyco:
>+	case ixgbe_phy_sfp_passive_unknown:
>+	case ixgbe_phy_qsfp_passive_unknown:
>+		physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
>+		break;
>+	case ixgbe_phy_sfp_ftl_active:
>+	case ixgbe_phy_sfp_active_unknown:
>+	case ixgbe_phy_qsfp_active_unknown:
>+		physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
>+		break;
>+	case ixgbe_phy_sfp_avago:
>+	case ixgbe_phy_sfp_ftl:
>+	case ixgbe_phy_sfp_intel:
>+	case ixgbe_phy_sfp_unknown:
>+		hw->phy.ops.read_i2c_eeprom(hw,
>+		      IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
>+		hw->phy.ops.read_i2c_eeprom(hw,
>+		      IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
>+		if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
>+			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
>+		else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
>+			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
>+		else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
>+			physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
>+		else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
>+			physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
>+		break;
>+	case ixgbe_phy_qsfp_intel:
>+	case ixgbe_phy_qsfp_unknown:
>+		hw->phy.ops.read_i2c_eeprom(hw,
>+		      IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
>+		if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
>+			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
>+		else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
>+			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
>+		break;
>+	default:
>+		break;
>+	}
>+
>+	return physical_layer;
>+}
>+
> /**
>+ *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
>+ *  @hw: pointer to hardware structure
>+ *
>+ *  Searches for and identifies the QSFP module and assigns appropriate PHY type
>+ **/
>+s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
>+{
>+	s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
>+	u32 vendor_oui = 0;
>+	enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
>+	u8 identifier = 0;
>+	u8 comp_codes_1g = 0;
>+	u8 comp_codes_10g = 0;
>+	u8 oui_bytes[3] = {0, 0, 0};
>+	u16 enforce_sfp = 0;
>+	u8 connector = 0;
>+	u8 cable_length = 0;
>+	u8 device_tech = 0;
>+	bool active_cable = FALSE;
>+
>+	DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
>+
>+	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
>+		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
>+		status = IXGBE_ERR_SFP_NOT_PRESENT;
>+		goto out;
>+	}
>+
>+	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
>+					     &identifier);
>+
>+	if (status != IXGBE_SUCCESS)
>+		goto err_read_i2c_eeprom;
>+
>+	if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
>+		hw->phy.type = ixgbe_phy_sfp_unsupported;
>+		status = IXGBE_ERR_SFP_NOT_SUPPORTED;
>+		goto out;
>+	}
>+
>+	hw->phy.id = identifier;
>+
>+	/* LAN ID is needed for sfp_type determination */
>+	hw->mac.ops.set_lan_id(hw);
>+
>+	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
>+					     &comp_codes_10g);
>+
>+	if (status != IXGBE_SUCCESS)
>+		goto err_read_i2c_eeprom;
>+
>+	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
>+					     &comp_codes_1g);
>+
>+	if (status != IXGBE_SUCCESS)
>+		goto err_read_i2c_eeprom;
>+
>+	if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
>+		hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
>+		if (hw->bus.lan_id == 0)
>+			hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
>+		else
>+			hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
>+	} else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
>+				     IXGBE_SFF_10GBASELR_CAPABLE)) {
>+		if (hw->bus.lan_id == 0)
>+			hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
>+		else
>+			hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
>+	} else {
>+		if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
>+			active_cable = TRUE;
>+
>+		if (!active_cable) {
>+			/* check for active DA cables that pre-date
>+			 * SFF-8436 v3.6 */
>+			hw->phy.ops.read_i2c_eeprom(hw,
>+					IXGBE_SFF_QSFP_CONNECTOR,
>+					&connector);
>+
>+			hw->phy.ops.read_i2c_eeprom(hw,
>+					IXGBE_SFF_QSFP_CABLE_LENGTH,
>+					&cable_length);
>+
>+			hw->phy.ops.read_i2c_eeprom(hw,
>+					IXGBE_SFF_QSFP_DEVICE_TECH,
>+					&device_tech);
>+
>+			if ((connector ==
>+				     IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
>+			    (cable_length > 0) &&
>+			    ((device_tech >> 4) ==
>+				     IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
>+				active_cable = TRUE;
>+		}
>+
>+		if (active_cable) {
>+			hw->phy.type = ixgbe_phy_qsfp_active_unknown;
>+			if (hw->bus.lan_id == 0)
>+				hw->phy.sfp_type =
>+						ixgbe_sfp_type_da_act_lmt_core0;
>+			else
>+				hw->phy.sfp_type =
>+						ixgbe_sfp_type_da_act_lmt_core1;
>+		} else {
>+			/* unsupported module type */
>+			hw->phy.type = ixgbe_phy_sfp_unsupported;
>+			status = IXGBE_ERR_SFP_NOT_SUPPORTED;
>+			goto out;
>+		}
>+	}
>+
>+	if (hw->phy.sfp_type != stored_sfp_type)
>+		hw->phy.sfp_setup_needed = TRUE;
>+
>+	/* Determine if the QSFP+ PHY is dual speed or not. */
>+	hw->phy.multispeed_fiber = FALSE;
>+	if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
>+	   (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
>+	   ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
>+	   (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
>+		hw->phy.multispeed_fiber = TRUE;
>+
>+	/* Determine PHY vendor for optical modules */
>+	if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
>+			      IXGBE_SFF_10GBASELR_CAPABLE))  {
>+		status = hw->phy.ops.read_i2c_eeprom(hw,
>+					    IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
>+					    &oui_bytes[0]);
>+
>+		if (status != IXGBE_SUCCESS)
>+			goto err_read_i2c_eeprom;
>+
>+		status = hw->phy.ops.read_i2c_eeprom(hw,
>+					    IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
>+					    &oui_bytes[1]);
>+
>+		if (status != IXGBE_SUCCESS)
>+			goto err_read_i2c_eeprom;
>+
>+		status = hw->phy.ops.read_i2c_eeprom(hw,
>+					    IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
>+					    &oui_bytes[2]);
>+
>+		if (status != IXGBE_SUCCESS)
>+			goto err_read_i2c_eeprom;
>+
>+		vendor_oui =
>+		  ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
>+		   (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
>+		   (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
>+
>+		if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
>+			hw->phy.type = ixgbe_phy_qsfp_intel;
>+		else
>+			hw->phy.type = ixgbe_phy_qsfp_unknown;
>+
>+		ixgbe_get_device_caps(hw, &enforce_sfp);
>+		if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
>+			/* Make sure we're a supported PHY type */
>+			if (hw->phy.type == ixgbe_phy_qsfp_intel) {
>+				status = IXGBE_SUCCESS;
>+			} else {
>+				if (hw->allow_unsupported_sfp == TRUE) {
>+					EWARN(hw, "WARNING: Intel (R) Network "
>+					      "Connections are quality tested "
>+					      "using Intel (R) Ethernet Optics."
>+					      " Using untested modules is not "
>+					      "supported and may cause unstable"
>+					      " operation or damage to the "
>+					      "module or the adapter. Intel "
>+					      "Corporation is not responsible "
>+					      "for any harm caused by using "
>+					      "untested modules.\n", status);
>+					status = IXGBE_SUCCESS;
>+				} else {
>+					DEBUGOUT("QSFP module not supported\n");
>+					hw->phy.type =
>+						ixgbe_phy_sfp_unsupported;
>+					status = IXGBE_ERR_SFP_NOT_SUPPORTED;
>+				}
>+			}
>+		} else {
>+			status = IXGBE_SUCCESS;
>+		}
>+	}
>+
>+out:
>+	return status;
>+
>+err_read_i2c_eeprom:
>+	hw->phy.sfp_type = ixgbe_sfp_type_not_present;
>+	hw->phy.id = 0;
>+	hw->phy.type = ixgbe_phy_unknown;
>+
>+	return IXGBE_ERR_SFP_NOT_PRESENT;
>+}
>+
>+
>+/**
>  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
>  *  @hw: pointer to hardware structure
>  *  @list_offset: offset to the SFP ID list
>@@ -1420,26 +1693,18 @@
> s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
> 				u8 dev_addr, u8 *data)
> {
>-	s32 status = IXGBE_SUCCESS;
>+	s32 status;
> 	u32 max_retry = 10;
> 	u32 retry = 0;
>-	u16 swfw_mask = 0;
>+	u32 swfw_mask = hw->phy.phy_semaphore_mask;
> 	bool nack = 1;
> 	*data = 0;
> 
> 	DEBUGFUNC("ixgbe_read_i2c_byte_generic");
> 
>-	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
>-		swfw_mask = IXGBE_GSSR_PHY1_SM;
>-	else
>-		swfw_mask = IXGBE_GSSR_PHY0_SM;
>-
> 	do {
>-		if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
>-		    != IXGBE_SUCCESS) {
>-			status = IXGBE_ERR_SWFW_SYNC;
>-			goto read_byte_out;
>-		}
>+		if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
>+			return IXGBE_ERR_SWFW_SYNC;
> 
> 		ixgbe_i2c_start(hw);
> 
>@@ -1480,7 +1745,8 @@
> 			goto fail;
> 
> 		ixgbe_i2c_stop(hw);
>-		break;
>+		hw->mac.ops.release_swfw_sync(hw, swfw_mask);
>+		return IXGBE_SUCCESS;
> 
> fail:
> 		ixgbe_i2c_bus_clear(hw);
>@@ -1494,9 +1760,6 @@
> 
> 	} while (retry < max_retry);
> 
>-	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
>-
>-read_byte_out:
> 	return status;
> }
> 
>@@ -1515,15 +1778,10 @@
> 	s32 status = IXGBE_SUCCESS;
> 	u32 max_retry = 1;
> 	u32 retry = 0;
>-	u16 swfw_mask = 0;
>+	u32 swfw_mask = hw->phy.phy_semaphore_mask;
> 
> 	DEBUGFUNC("ixgbe_write_i2c_byte_generic");
> 
>-	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
>-		swfw_mask = IXGBE_GSSR_PHY1_SM;
>-	else
>-		swfw_mask = IXGBE_GSSR_PHY0_SM;
>-
> 	if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
> 		status = IXGBE_ERR_SWFW_SYNC;
> 		goto write_byte_out;
>@@ -1557,7 +1815,8 @@
> 			goto fail;
> 
> 		ixgbe_i2c_stop(hw);
>-		break;
>+		hw->mac.ops.release_swfw_sync(hw, swfw_mask);
>+		return IXGBE_SUCCESS;
> 
> fail:
> 		ixgbe_i2c_bus_clear(hw);
>@@ -1582,10 +1841,12 @@
>  **/
> static void ixgbe_i2c_start(struct ixgbe_hw *hw)
> {
>-	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
>+	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
> 
> 	DEBUGFUNC("ixgbe_i2c_start");
> 
>+	i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
>+
> 	/* Start condition must begin with data and clock high */
> 	ixgbe_set_i2c_data(hw, &i2cctl, 1);
> 	ixgbe_raise_i2c_clk(hw, &i2cctl);
>@@ -1613,7 +1874,10 @@
>  **/
> static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
> {
>-	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
>+	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
>+	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
>+	u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
>+	u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
> 
> 	DEBUGFUNC("ixgbe_i2c_stop");
> 
>@@ -1628,6 +1892,13 @@
> 
> 	/* bus free time between stop and start (4.7us)*/
> 	usec_delay(IXGBE_I2C_T_BUF);
>+
>+	if (bb_en_bit || data_oe_bit || clk_oe_bit) {
>+		i2cctl &= ~bb_en_bit;
>+		i2cctl |= data_oe_bit | clk_oe_bit;
>+		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
>+		IXGBE_WRITE_FLUSH(hw);
>+	}
> }
> 
> /**
>@@ -1644,6 +1915,7 @@
> 
> 	DEBUGFUNC("ixgbe_clock_in_i2c_byte");
> 
>+	*data = 0;
> 	for (i = 7; i >= 0; i--) {
> 		ixgbe_clock_in_i2c_bit(hw, &bit);
> 		*data |= bit << i;
>@@ -1664,7 +1936,7 @@
> 	s32 status = IXGBE_SUCCESS;
> 	s32 i;
> 	u32 i2cctl;
>-	bool bit = 0;
>+	bool bit;
> 
> 	DEBUGFUNC("ixgbe_clock_out_i2c_byte");
> 
>@@ -1677,9 +1949,10 @@
> 	}
> 
> 	/* Release SDA line (set high) */
>-	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
>-	i2cctl |= IXGBE_I2C_DATA_OUT;
>-	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
>+	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
>+	i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
>+	i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
>+	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
> 	IXGBE_WRITE_FLUSH(hw);
> 
> 	return status;
>@@ -1693,17 +1966,23 @@
>  **/
> static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
> {
>+	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
> 	s32 status = IXGBE_SUCCESS;
> 	u32 i = 0;
>-	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
>+	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
> 	u32 timeout = 10;
> 	bool ack = 1;
> 
> 	DEBUGFUNC("ixgbe_get_i2c_ack");
> 
>+	if (data_oe_bit) {
>+		i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
>+		i2cctl |= data_oe_bit;
>+		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
>+		IXGBE_WRITE_FLUSH(hw);
>+	}
> 	ixgbe_raise_i2c_clk(hw, &i2cctl);
> 
>-
> 	/* Minimum high period of clock is 4us */
> 	usec_delay(IXGBE_I2C_T_HIGH);
> 
>@@ -1710,17 +1989,16 @@
> 	/* Poll for ACK.  Note that ACK in I2C spec is
> 	 * transition from 1 to 0 */
> 	for (i = 0; i < timeout; i++) {
>-		i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
>-		ack = ixgbe_get_i2c_data(&i2cctl);
>+		i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
>+		ack = ixgbe_get_i2c_data(hw, &i2cctl);
> 
> 		usec_delay(1);
>-		if (ack == 0)
>+		if (!ack)
> 			break;
> 	}
> 
>-	if (ack == 1) {
>-		ERROR_REPORT1(IXGBE_ERROR_POLLING,
>-			     "I2C ack was not received.\n");
>+	if (ack) {
>+		DEBUGOUT("I2C ack was not received.\n");
> 		status = IXGBE_ERR_I2C;
> 	}
> 
>@@ -1741,17 +2019,24 @@
>  **/
> static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
> {
>-	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
>+	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
>+	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
> 
> 	DEBUGFUNC("ixgbe_clock_in_i2c_bit");
> 
>+	if (data_oe_bit) {
>+		i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
>+		i2cctl |= data_oe_bit;
>+		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
>+		IXGBE_WRITE_FLUSH(hw);
>+	}
> 	ixgbe_raise_i2c_clk(hw, &i2cctl);
> 
> 	/* Minimum high period of clock is 4us */
> 	usec_delay(IXGBE_I2C_T_HIGH);
> 
>-	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
>-	*data = ixgbe_get_i2c_data(&i2cctl);
>+	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
>+	*data = ixgbe_get_i2c_data(hw, &i2cctl);
> 
> 	ixgbe_lower_i2c_clk(hw, &i2cctl);
> 
>@@ -1771,7 +2056,7 @@
> static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
> {
> 	s32 status;
>-	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
>+	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
> 
> 	DEBUGFUNC("ixgbe_clock_out_i2c_bit");
> 
>@@ -1796,6 +2081,7 @@
> 
> 	return status;
> }
>+
> /**
>  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
>  *  @hw: pointer to hardware structure
>@@ -1805,6 +2091,7 @@
>  **/
> static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
> {
>+	u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
> 	u32 i = 0;
> 	u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
> 	u32 i2cctl_r = 0;
>@@ -1811,16 +2098,21 @@
> 
> 	DEBUGFUNC("ixgbe_raise_i2c_clk");
> 
>+	if (clk_oe_bit) {
>+		*i2cctl |= clk_oe_bit;
>+		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
>+	}
>+
> 	for (i = 0; i < timeout; i++) {
>-		*i2cctl |= IXGBE_I2C_CLK_OUT;
>+		*i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
> 
>-		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
>+		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
> 		IXGBE_WRITE_FLUSH(hw);
> 		/* SCL rise time (1000ns) */
> 		usec_delay(IXGBE_I2C_T_RISE);
> 
>-		i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
>-		if (i2cctl_r & IXGBE_I2C_CLK_IN)
>+		i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
>+		if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
> 			break;
> 	}
> }
>@@ -1834,12 +2126,12 @@
>  **/
> static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
> {
>-
> 	DEBUGFUNC("ixgbe_lower_i2c_clk");
> 
>-	*i2cctl &= ~IXGBE_I2C_CLK_OUT;
>+	*i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
>+	*i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
> 
>-	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
>+	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
> 	IXGBE_WRITE_FLUSH(hw);
> 
> 	/* SCL fall time (300ns) */
>@@ -1856,24 +2148,34 @@
>  **/
> static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
> {
>+	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
> 	s32 status = IXGBE_SUCCESS;
> 
> 	DEBUGFUNC("ixgbe_set_i2c_data");
> 
> 	if (data)
>-		*i2cctl |= IXGBE_I2C_DATA_OUT;
>+		*i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
> 	else
>-		*i2cctl &= ~IXGBE_I2C_DATA_OUT;
>+		*i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
>+	*i2cctl &= ~data_oe_bit;
> 
>-	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
>+	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
> 	IXGBE_WRITE_FLUSH(hw);
> 
> 	/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
> 	usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
> 
>+	if (!data)	/* Can't verify data in this case */
>+		return IXGBE_SUCCESS;
>+	if (data_oe_bit) {
>+		*i2cctl |= data_oe_bit;
>+		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
>+		IXGBE_WRITE_FLUSH(hw);
>+	}
>+
> 	/* Verify data was set correctly */
>-	*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
>-	if (data != ixgbe_get_i2c_data(i2cctl)) {
>+	*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
>+	if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
> 		status = IXGBE_ERR_I2C;
> 		ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
> 			     "Error - I2C data was not set to %X.\n",
>@@ -1890,13 +2192,22 @@
>  *
>  *  Returns the I2C data bit value
>  **/
>-static bool ixgbe_get_i2c_data(u32 *i2cctl)
>+static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
> {
>+	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
> 	bool data;
>+	UNREFERENCED_1PARAMETER(hw);
> 
> 	DEBUGFUNC("ixgbe_get_i2c_data");
> 
>-	if (*i2cctl & IXGBE_I2C_DATA_IN)
>+	if (data_oe_bit) {
>+		*i2cctl |= data_oe_bit;
>+		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
>+		IXGBE_WRITE_FLUSH(hw);
>+		usec_delay(IXGBE_I2C_T_FALL);
>+	}
>+
>+	if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
> 		data = 1;
> 	else
> 		data = 0;
>@@ -1913,12 +2224,13 @@
>  **/
> void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
> {
>-	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
>+	u32 i2cctl;
> 	u32 i;
> 
> 	DEBUGFUNC("ixgbe_i2c_bus_clear");
> 
> 	ixgbe_i2c_start(hw);
>+	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
> 
> 	ixgbe_set_i2c_data(hw, &i2cctl, 1);
> 
>Index: ixgbe_phy.h
>===================================================================
>--- ixgbe_phy.h	(revision 273551)
>+++ ixgbe_phy.h	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>@@ -54,6 +54,15 @@
> #define IXGBE_SFF_SFF_8472_COMP		0x5E
> #define IXGBE_SFF_SFF_8472_OSCB		0x6E
> #define IXGBE_SFF_SFF_8472_ESCB		0x76
>+#define IXGBE_SFF_IDENTIFIER_QSFP_PLUS	0xD
>+#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0	0xA5
>+#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1	0xA6
>+#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2	0xA7
>+#define IXGBE_SFF_QSFP_CONNECTOR	0x82
>+#define IXGBE_SFF_QSFP_10GBE_COMP	0x83
>+#define IXGBE_SFF_QSFP_1GBE_COMP	0x86
>+#define IXGBE_SFF_QSFP_CABLE_LENGTH	0x92
>+#define IXGBE_SFF_QSFP_DEVICE_TECH	0x93
> 
> /* Bitmasks */
> #define IXGBE_SFF_DA_PASSIVE_CABLE	0x4
>@@ -67,6 +76,11 @@
> #define IXGBE_SFF_SOFT_RS_SELECT_MASK	0x8
> #define IXGBE_SFF_SOFT_RS_SELECT_10G	0x8
> #define IXGBE_SFF_SOFT_RS_SELECT_1G	0x0
>+#define IXGBE_SFF_ADDRESSING_MODE	0x4
>+#define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE	0x1
>+#define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE	0x8
>+#define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE	0x23
>+#define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL	0x0
> #define IXGBE_I2C_EEPROM_READ_MASK	0x100
> #define IXGBE_I2C_EEPROM_STATUS_MASK	0x3
> #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION	0x0
>@@ -106,11 +120,6 @@
> 
> /* SFP+ SFF-8472 Compliance */
> #define IXGBE_SFF_SFF_8472_UNSUP	0x00
>-#define IXGBE_SFF_SFF_8472_REV_9_3	0x01
>-#define IXGBE_SFF_SFF_8472_REV_9_5	0x02
>-#define IXGBE_SFF_SFF_8472_REV_10_2	0x03
>-#define IXGBE_SFF_SFF_8472_REV_10_4	0x04
>-#define IXGBE_SFF_SFF_8472_REV_11_0	0x05
> 
> s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
> bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
>@@ -133,6 +142,7 @@
> s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
> 					       ixgbe_link_speed *speed,
> 					       bool *autoneg);
>+s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw);
> 
> /* PHY specific */
> s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
>@@ -147,6 +157,8 @@
> s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
> s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
> s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
>+s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw);
>+s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
> s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
> 					u16 *list_offset,
> 					u16 *data_offset);
>Index: ixgbe_type.h
>===================================================================
>--- ixgbe_type.h	(revision 273551)
>+++ ixgbe_type.h	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>@@ -75,6 +75,8 @@
> 
> #include "ixgbe_osdep.h"
> 
>+/* Override this by setting IOMEM in your ixgbe_osdep.h header */
>+#define IOMEM
> 
> /* Vendor ID */
> #define IXGBE_INTEL_VENDOR_ID			0x8086
>@@ -100,16 +102,21 @@
> #define IXGBE_DEV_ID_82599_CX4			0x10F9
> #define IXGBE_DEV_ID_82599_SFP			0x10FB
> #define IXGBE_SUBDEV_ID_82599_SFP		0x11A9
>+#define IXGBE_SUBDEV_ID_82599_SFP_WOL0		0x1071
> #define IXGBE_SUBDEV_ID_82599_RNDC		0x1F72
> #define IXGBE_SUBDEV_ID_82599_560FLR		0x17D0
> #define IXGBE_SUBDEV_ID_82599_ECNA_DP		0x0470
> #define IXGBE_SUBDEV_ID_82599_SP_560FLR		0x211B
> #define IXGBE_SUBDEV_ID_82599_LOM_SFP		0x8976
>+#define IXGBE_SUBDEV_ID_82599_LOM_SNAP6		0x2159
>+#define IXGBE_SUBDEV_ID_82599_SFP_1OCP		0x000D
>+#define IXGBE_SUBDEV_ID_82599_SFP_2OCP		0x0008
> #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE	0x152A
> #define IXGBE_DEV_ID_82599_SFP_FCOE		0x1529
> #define IXGBE_DEV_ID_82599_SFP_EM		0x1507
> #define IXGBE_DEV_ID_82599_SFP_SF2		0x154D
> #define IXGBE_DEV_ID_82599_SFP_SF_QP		0x154A
>+#define IXGBE_DEV_ID_82599_QSFP_SF_QP		0x1558
> #define IXGBE_DEV_ID_82599EN_SFP		0x1557
> #define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1	0x0001
> #define IXGBE_DEV_ID_82599_XAUI_LOM		0x10FC
>@@ -121,6 +128,7 @@
> #define IXGBE_DEV_ID_X540_VF			0x1515
> #define IXGBE_DEV_ID_X540_VF_HV			0x1530
> #define IXGBE_DEV_ID_X540_BYPASS		0x155C
>+#define IXGBE_DEV_ID_X540T1			0x1560
> 
> /* General Registers */
> #define IXGBE_CTRL		0x00000
>@@ -128,7 +136,8 @@
> #define IXGBE_CTRL_EXT		0x00018
> #define IXGBE_ESDP		0x00020
> #define IXGBE_EODSDP		0x00028
>-#define IXGBE_I2CCTL		0x00028
>+#define IXGBE_I2CCTL_82599	0x00028
>+#define IXGBE_I2CCTL_BY_MAC(_hw)(0x00028)
> #define IXGBE_PHY_GPIO		0x00028
> #define IXGBE_MAC_GPIO		0x00030
> #define IXGBE_PHYINT_STATUS0	0x00100
>@@ -163,10 +172,13 @@
> #define IXGBE_VPDDIAG1	0x10208
> 
> /* I2CCTL Bit Masks */
>-#define IXGBE_I2C_CLK_IN	0x00000001
>-#define IXGBE_I2C_CLK_OUT	0x00000002
>-#define IXGBE_I2C_DATA_IN	0x00000004
>-#define IXGBE_I2C_DATA_OUT	0x00000008
>+#define IXGBE_I2C_CLK_IN_BY_MAC(_hw)(0x00000001)
>+#define IXGBE_I2C_CLK_OUT_BY_MAC(_hw)(0x00000002)
>+#define IXGBE_I2C_DATA_IN_BY_MAC(_hw)(0x00000004)
>+#define IXGBE_I2C_DATA_OUT_BY_MAC(_hw)(0x00000008)
>+#define IXGBE_I2C_BB_EN_BY_MAC(hw) 0
>+#define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw) 0
>+#define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw) 0
> #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT	500
> 
> 
>@@ -336,6 +348,7 @@
> #define IXGBE_FDIRSIP4M	0x0EE40
> #define IXGBE_FDIRTCPM	0x0EE44
> #define IXGBE_FDIRUDPM	0x0EE48
>+#define IXGBE_FDIRSCTPM	0x0EE78
> #define IXGBE_FDIRIP6M	0x0EE74
> #define IXGBE_FDIRM	0x0EE70
> 
>@@ -409,9 +422,9 @@
> #define IXGBE_WUPL	0x05900
> #define IXGBE_WUPM	0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
> 
>-#define IXGBE_FHFT(_n)	(0x09000 + (_n * 0x100)) /* Flex host filter table */
>+#define IXGBE_FHFT(_n)	(0x09000 + ((_n) * 0x100)) /* Flex host filter table */
> /* Ext Flexible Host Filter Table */
>-#define IXGBE_FHFT_EXT(_n)	(0x09800 + (_n * 0x100))
>+#define IXGBE_FHFT_EXT(_n)	(0x09800 + ((_n) * 0x100))
> 
> /* Four Flexible Filters are supported */
> #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX		4
>@@ -781,11 +794,6 @@
> #define IXGBE_BXOFFRXC		0x041E0
> #define IXGBE_BXONTXC		0x041E4
> #define IXGBE_BXOFFTXC		0x041E8
>-#define IXGBE_PCRC8ECL		0x0E810
>-#define IXGBE_PCRC8ECH		0x0E811
>-#define IXGBE_PCRC8ECH_MASK	0x1F
>-#define IXGBE_LDPCECL		0x0E820
>-#define IXGBE_LDPCECH		0x0E821
> 
> /* Management */
> #define IXGBE_MAVTV(_i)		(0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
>@@ -869,6 +877,8 @@
> #define IXGBE_PBACLR_82599	0x11068
> #define IXGBE_CIAA_82599	0x11088
> #define IXGBE_CIAD_82599	0x1108C
>+#define IXGBE_CIAA_BY_MAC(_hw)	(IXGBE_CIAA_82599)
>+#define IXGBE_CIAD_BY_MAC(_hw)	(IXGBE_CIAD_82599)
> #define IXGBE_PICAUSE		0x110B0
> #define IXGBE_PIENA		0x110B8
> #define IXGBE_CDQ_MBR_82599	0x110B4
>@@ -1209,8 +1219,13 @@
> 
> #define IXGBE_MDIO_AUTO_NEG_CONTROL	0x0 /* AUTO_NEG Control Reg */
> #define IXGBE_MDIO_AUTO_NEG_STATUS	0x1 /* AUTO_NEG Status Reg */
>+#define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT	0xC800 /* AUTO_NEG Vendor Status Reg */
> #define IXGBE_MDIO_AUTO_NEG_ADVT	0x10 /* AUTO_NEG Advt Reg */
> #define IXGBE_MDIO_AUTO_NEG_LP		0x13 /* AUTO_NEG LP Status Reg */
>+#define IXGBE_MDIO_AUTO_NEG_EEE_ADVT	0x3C /* AUTO_NEG EEE Advt Reg */
>+#define IXGBE_AUTO_NEG_10GBASE_EEE_ADVT	0x8  /* AUTO NEG EEE 10GBaseT Advt */
>+#define IXGBE_AUTO_NEG_1000BASE_EEE_ADVT 0x4  /* AUTO NEG EEE 1000BaseT Advt */
>+#define IXGBE_AUTO_NEG_100BASE_EEE_ADVT	0x2  /* AUTO NEG EEE 100BaseT Advt */
> #define IXGBE_MDIO_PHY_XS_CONTROL	0x0 /* PHY_XS Control Reg */
> #define IXGBE_MDIO_PHY_XS_RESET		0x8000 /* PHY_XS Reset */
> #define IXGBE_MDIO_PHY_ID_HIGH		0x2 /* PHY ID High Reg*/
>@@ -1225,14 +1240,42 @@
> #define IXGBE_MDIO_PHY_100BASETX_ABILITY	0x0080 /* 100BaseTX capable */
> #define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE	0x0800 /* Set low power mode */
> 
>+#define IXGBE_MDIO_TX_VENDOR_ALARMS_3		0xCC02 /* Vendor Alarms 3 Reg */
>+#define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK	0x3 /* PHY Reset Complete Mask */
>+#define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479 /* Global Resv Provisioning 10 Reg */
>+#define IXGBE_MDIO_POWER_UP_STALL		0x8000 /* Power Up Stall */
>+
> #define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR	0x0000 /* PMA/PMD Control Reg */
> #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR	0xC30A /* PHY_XS SDA/SCL Addr Reg */
> #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA	0xC30B /* PHY_XS SDA/SCL Data Reg */
> #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT	0xC30C /* PHY_XS SDA/SCL Status Reg */
>+#define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Transmit Dis Reg */
>+#define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Transmit Dis */
> 
>+#define IXGBE_PCRC8ECL		0x0E810 /* PCR CRC-8 Error Count Lo */
>+#define IXGBE_PCRC8ECH		0x0E811 /* PCR CRC-8 Error Count Hi */
>+#define IXGBE_PCRC8ECH_MASK	0x1F
>+#define IXGBE_LDPCECL		0x0E820 /* PCR Uncorrected Error Count Lo */
>+#define IXGBE_LDPCECH		0x0E821 /* PCR Uncorrected Error Count Hi */
>+
> /* MII clause 22/28 definitions */
> #define IXGBE_MDIO_PHY_LOW_POWER_MODE	0x0800
> 
>+#define IXGBE_MDIO_XENPAK_LASI_STATUS		0x9005 /* XENPAK LASI Status register*/
>+#define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM	0x1 /* Link Status Alarm change */
>+
>+#define IXGBE_MDIO_AUTO_NEG_LINK_STATUS		0x4 /* Indicates if link is up */
>+
>+#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK		0x7 /* Speed/Duplex Mask */
>+#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF	0x0 /* 10Mb/s Half Duplex */
>+#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL	0x1 /* 10Mb/s Full Duplex */
>+#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF	0x2 /* 100Mb/s Half Duplex */
>+#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL	0x3 /* 100Mb/s Full Duplex */
>+#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF	0x4 /* 1Gb/s Half Duplex */
>+#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL	0x5 /* 1Gb/s Full Duplex */
>+#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF	0x6 /* 10Gb/s Half Duplex */
>+#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL	0x7 /* 10Gb/s Full Duplex */
>+
> #define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG	0x20   /* 10G Control Reg */
> #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
> #define IXGBE_MII_AUTONEG_XNP_TX_REG		0x17   /* 1G XNP Transmit */
>@@ -1240,6 +1283,8 @@
> #define IXGBE_MII_10GBASE_T_ADVERTISE		0x1000 /* full duplex, bit:12*/
> #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX	0x4000 /* full duplex, bit:14*/
> #define IXGBE_MII_1GBASE_T_ADVERTISE		0x8000 /* full duplex, bit:15*/
>+#define IXGBE_MII_2_5GBASE_T_ADVERTISE		0x0400
>+#define IXGBE_MII_5GBASE_T_ADVERTISE		0x0800
> #define IXGBE_MII_100BASE_T_ADVERTISE		0x0100 /* full duplex, bit:8 */
> #define IXGBE_MII_100BASE_T_ADVERTISE_HALF	0x0080 /* half duplex, bit:7 */
> #define IXGBE_MII_RESTART			0x200
>@@ -1607,11 +1652,15 @@
>  *	FCoE (0x8906):	 Filter 2
>  *	1588 (0x88f7):	 Filter 3
>  *	FIP  (0x8914):	 Filter 4
>+ *	LLDP (0x88CC):	 Filter 5
>+ *	LACP (0x8809):	 Filter 6
>  */
> #define IXGBE_ETQF_FILTER_EAPOL		0
> #define IXGBE_ETQF_FILTER_FCOE		2
> #define IXGBE_ETQF_FILTER_1588		3
> #define IXGBE_ETQF_FILTER_FIP		4
>+#define IXGBE_ETQF_FILTER_LLDP		5
>+#define IXGBE_ETQF_FILTER_LACP		6
> /* VLAN Control Bit Masks */
> #define IXGBE_VLNCTRL_VET		0x0000FFFF  /* bits 0-15 */
> #define IXGBE_VLNCTRL_CFI		0x10000000  /* bit 28 */
>@@ -1735,6 +1784,9 @@
> #define IXGBE_MACC_FS		0x00040000
> #define IXGBE_MAC_RX2TX_LPBK	0x00000002
> 
>+/* Veto Bit definiton */
>+#define IXGBE_MMNGC_MNG_VETO	0x00000001
>+
> /* LINKS Bit Masks */
> #define IXGBE_LINKS_KX_AN_COMP	0x80000000
> #define IXGBE_LINKS_UP		0x40000000
>@@ -1795,12 +1847,14 @@
> #define IXGBE_SWFW_REGSMP	0x80000000 /* Register Semaphore bit 31 */
> 
> /* SW_FW_SYNC/GSSR definitions */
>-#define IXGBE_GSSR_EEP_SM	0x0001
>-#define IXGBE_GSSR_PHY0_SM	0x0002
>-#define IXGBE_GSSR_PHY1_SM	0x0004
>-#define IXGBE_GSSR_MAC_CSR_SM	0x0008
>-#define IXGBE_GSSR_FLASH_SM	0x0010
>-#define IXGBE_GSSR_SW_MNG_SM	0x0400
>+#define IXGBE_GSSR_EEP_SM		0x0001
>+#define IXGBE_GSSR_PHY0_SM		0x0002
>+#define IXGBE_GSSR_PHY1_SM		0x0004
>+#define IXGBE_GSSR_MAC_CSR_SM		0x0008
>+#define IXGBE_GSSR_FLASH_SM		0x0010
>+#define IXGBE_GSSR_NVM_UPDATE_SM	0x0200
>+#define IXGBE_GSSR_SW_MNG_SM		0x0400
>+#define IXGBE_GSSR_NVM_PHY_MASK	0xF
> 
> /* FW Status register bitmask */
> #define IXGBE_FWSTS_FWRI	0x00000200 /* Firmware Reset Indication */
>@@ -1834,28 +1888,28 @@
> #define IXGBE_PBANUM_LENGTH	11
> 
> /* Checksum and EEPROM pointers */
>-#define IXGBE_PBANUM_PTR_GUARD	0xFAFA
>-#define IXGBE_EEPROM_CHECKSUM	0x3F
>-#define IXGBE_EEPROM_SUM	0xBABA
>-#define IXGBE_PCIE_ANALOG_PTR	0x03
>-#define IXGBE_ATLAS0_CONFIG_PTR	0x04
>-#define IXGBE_PHY_PTR		0x04
>-#define IXGBE_ATLAS1_CONFIG_PTR	0x05
>-#define IXGBE_OPTION_ROM_PTR	0x05
>-#define IXGBE_PCIE_GENERAL_PTR	0x06
>-#define IXGBE_PCIE_CONFIG0_PTR	0x07
>-#define IXGBE_PCIE_CONFIG1_PTR	0x08
>-#define IXGBE_CORE0_PTR		0x09
>-#define IXGBE_CORE1_PTR		0x0A
>-#define IXGBE_MAC0_PTR		0x0B
>-#define IXGBE_MAC1_PTR		0x0C
>-#define IXGBE_CSR0_CONFIG_PTR	0x0D
>-#define IXGBE_CSR1_CONFIG_PTR	0x0E
>-#define IXGBE_FW_PTR		0x0F
>-#define IXGBE_PBANUM0_PTR	0x15
>-#define IXGBE_PBANUM1_PTR	0x16
>-#define IXGBE_ALT_MAC_ADDR_PTR	0x37
>-#define IXGBE_FREE_SPACE_PTR	0X3E
>+#define IXGBE_PBANUM_PTR_GUARD		0xFAFA
>+#define IXGBE_EEPROM_CHECKSUM		0x3F
>+#define IXGBE_EEPROM_SUM		0xBABA
>+#define IXGBE_PCIE_ANALOG_PTR		0x03
>+#define IXGBE_ATLAS0_CONFIG_PTR		0x04
>+#define IXGBE_PHY_PTR			0x04
>+#define IXGBE_ATLAS1_CONFIG_PTR		0x05
>+#define IXGBE_OPTION_ROM_PTR		0x05
>+#define IXGBE_PCIE_GENERAL_PTR		0x06
>+#define IXGBE_PCIE_CONFIG0_PTR		0x07
>+#define IXGBE_PCIE_CONFIG1_PTR		0x08
>+#define IXGBE_CORE0_PTR			0x09
>+#define IXGBE_CORE1_PTR			0x0A
>+#define IXGBE_MAC0_PTR			0x0B
>+#define IXGBE_MAC1_PTR			0x0C
>+#define IXGBE_CSR0_CONFIG_PTR		0x0D
>+#define IXGBE_CSR1_CONFIG_PTR		0x0E
>+#define IXGBE_FW_PTR			0x0F
>+#define IXGBE_PBANUM0_PTR		0x15
>+#define IXGBE_PBANUM1_PTR		0x16
>+#define IXGBE_ALT_MAC_ADDR_PTR		0x37
>+#define IXGBE_FREE_SPACE_PTR		0X3E
> 
> #define IXGBE_SAN_MAC_ADDR_PTR		0x28
> #define IXGBE_DEVICE_CAPS		0x2C
>@@ -2010,7 +2064,7 @@
> #define IXGBE_RFCTL_ISCSI_DIS		0x00000001
> #define IXGBE_RFCTL_ISCSI_DWC_MASK	0x0000003E
> #define IXGBE_RFCTL_ISCSI_DWC_SHIFT	1
>-#define IXGBE_RFCTL_RSC_DIS		0x00000010
>+#define IXGBE_RFCTL_RSC_DIS		0x00000020
> #define IXGBE_RFCTL_NFSW_DIS		0x00000040
> #define IXGBE_RFCTL_NFSR_DIS		0x00000080
> #define IXGBE_RFCTL_NFS_VER_MASK	0x00000300
>@@ -2222,6 +2276,10 @@
> 
> /* SRRCTL bit definitions */
> #define IXGBE_SRRCTL_BSIZEPKT_SHIFT	10 /* so many KBs */
>+#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT	2 /* 64byte resolution (>> 6)
>+					   * + at bit 8 offset (<< 8)
>+					   *  = (<< 2)
>+					   */
> #define IXGBE_SRRCTL_RDMTS_SHIFT	22
> #define IXGBE_SRRCTL_RDMTS_MASK		0x01C00000
> #define IXGBE_SRRCTL_DROP_EN		0x10000000
>@@ -2319,7 +2377,69 @@
> #define IXGBE_MBVFICR(_i)		(0x00710 + ((_i) * 4))
> #define IXGBE_VFLRE(_i)			(((_i & 1) ? 0x001C0 : 0x00600))
> #define IXGBE_VFLREC(_i)		 (0x00700 + ((_i) * 4))
>+/* Translated register #defines */
>+#define IXGBE_PVFCTRL(P)	(0x00300 + (4 * (P)))
>+#define IXGBE_PVFSTATUS(P)	(0x00008 + (0 * (P)))
>+#define IXGBE_PVFLINKS(P)	(0x042A4 + (0 * (P)))
>+#define IXGBE_PVFRTIMER(P)	(0x00048 + (0 * (P)))
>+#define IXGBE_PVFMAILBOX(P)	(0x04C00 + (4 * (P)))
>+#define IXGBE_PVFRXMEMWRAP(P)	(0x03190 + (0 * (P)))
>+#define IXGBE_PVTEICR(P)	(0x00B00 + (4 * (P)))
>+#define IXGBE_PVTEICS(P)	(0x00C00 + (4 * (P)))
>+#define IXGBE_PVTEIMS(P)	(0x00D00 + (4 * (P)))
>+#define IXGBE_PVTEIMC(P)	(0x00E00 + (4 * (P)))
>+#define IXGBE_PVTEIAC(P)	(0x00F00 + (4 * (P)))
>+#define IXGBE_PVTEIAM(P)	(0x04D00 + (4 * (P)))
>+#define IXGBE_PVTEITR(P)	(((P) < 24) ? (0x00820 + ((P) * 4)) : \
>+				 (0x012300 + (((P) - 24) * 4)))
>+#define IXGBE_PVTIVAR(P)	(0x12500 + (4 * (P)))
>+#define IXGBE_PVTIVAR_MISC(P)	(0x04E00 + (4 * (P)))
>+#define IXGBE_PVTRSCINT(P)	(0x12000 + (4 * (P)))
>+#define IXGBE_VFPBACL(P)	(0x110C8 + (4 * (P)))
>+#define IXGBE_PVFRDBAL(P)	((P < 64) ? (0x01000 + (0x40 * (P))) \
>+				 : (0x0D000 + (0x40 * ((P) - 64))))
>+#define IXGBE_PVFRDBAH(P)	((P < 64) ? (0x01004 + (0x40 * (P))) \
>+				 : (0x0D004 + (0x40 * ((P) - 64))))
>+#define IXGBE_PVFRDLEN(P)	((P < 64) ? (0x01008 + (0x40 * (P))) \
>+				 : (0x0D008 + (0x40 * ((P) - 64))))
>+#define IXGBE_PVFRDH(P)		((P < 64) ? (0x01010 + (0x40 * (P))) \
>+				 : (0x0D010 + (0x40 * ((P) - 64))))
>+#define IXGBE_PVFRDT(P)		((P < 64) ? (0x01018 + (0x40 * (P))) \
>+				 : (0x0D018 + (0x40 * ((P) - 64))))
>+#define IXGBE_PVFRXDCTL(P)	((P < 64) ? (0x01028 + (0x40 * (P))) \
>+				 : (0x0D028 + (0x40 * ((P) - 64))))
>+#define IXGBE_PVFSRRCTL(P)	((P < 64) ? (0x01014 + (0x40 * (P))) \
>+				 : (0x0D014 + (0x40 * ((P) - 64))))
>+#define IXGBE_PVFPSRTYPE(P)	(0x0EA00 + (4 * (P)))
>+#define IXGBE_PVFTDBAL(P)	(0x06000 + (0x40 * (P)))
>+#define IXGBE_PVFTDBAH(P)	(0x06004 + (0x40 * (P)))
>+#define IXGBE_PVFTTDLEN(P)	(0x06008 + (0x40 * (P)))
>+#define IXGBE_PVFTDH(P)		(0x06010 + (0x40 * (P)))
>+#define IXGBE_PVFTDT(P)		(0x06018 + (0x40 * (P)))
>+#define IXGBE_PVFTXDCTL(P)	(0x06028 + (0x40 * (P)))
>+#define IXGBE_PVFTDWBAL(P)	(0x06038 + (0x40 * (P)))
>+#define IXGBE_PVFTDWBAH(P)	(0x0603C + (0x40 * (P)))
>+#define IXGBE_PVFDCA_RXCTRL(P)	(((P) < 64) ? (0x0100C + (0x40 * (P))) \
>+				 : (0x0D00C + (0x40 * ((P) - 64))))
>+#define IXGBE_PVFDCA_TXCTRL(P)	(0x0600C + (0x40 * (P)))
>+#define IXGBE_PVFGPRC(x)	(0x0101C + (0x40 * (x)))
>+#define IXGBE_PVFGPTC(x)	(0x08300 + (0x04 * (x)))
>+#define IXGBE_PVFGORC_LSB(x)	(0x01020 + (0x40 * (x)))
>+#define IXGBE_PVFGORC_MSB(x)	(0x0D020 + (0x40 * (x)))
>+#define IXGBE_PVFGOTC_LSB(x)	(0x08400 + (0x08 * (x)))
>+#define IXGBE_PVFGOTC_MSB(x)	(0x08404 + (0x08 * (x)))
>+#define IXGBE_PVFMPRC(x)	(0x0D01C + (0x40 * (x)))
> 
>+#define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \
>+		(IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index)))
>+#define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \
>+		(IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))
>+
>+#define IXGBE_PVFTDHn(q_per_pool, vf_number, vf_q_index) \
>+		(IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index)))
>+#define IXGBE_PVFTDTn(q_per_pool, vf_number, vf_q_index) \
>+		(IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index)))
>+
> /* Little Endian defines */
> #ifndef __le16
> #define __le16  u16
>@@ -2356,6 +2476,7 @@
> #define IXGBE_FDIRCTRL_DROP_Q_SHIFT		8
> #define IXGBE_FDIRCTRL_FLEX_SHIFT		16
> #define IXGBE_FDIRCTRL_SEARCHLIM		0x00800000
>+#define IXGBE_FDIRCTRL_FILTERMODE_MASK		0x00E00000
> #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT		24
> #define IXGBE_FDIRCTRL_FULL_THRESH_MASK		0xF0000000
> #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT	28
>@@ -2410,26 +2531,21 @@
> #define IXGBE_FDIRCMD_QUEUE_EN			0x00008000
> #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT		5
> #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT		16
>+#define IXGBE_FDIRCMD_TUNNEL_FILTER_SHIFT	23
> #define IXGBE_FDIRCMD_VT_POOL_SHIFT		24
> #define IXGBE_FDIR_INIT_DONE_POLL		10
> #define IXGBE_FDIRCMD_CMD_POLL			10
>-
>+#define IXGBE_FDIRCMD_TUNNEL_FILTER		0x00800000
> #define IXGBE_FDIR_DROP_QUEUE			127
> 
>-#define IXGBE_STATUS_OVERHEATING_BIT		20 /* STATUS overtemp bit num */
>-/* iTS sensor related defines*/
>-#define IXGBE_TEMP_STATUS_ADDR_X540		0xC830
>-#define IXGBE_TEMP_VALUE_ADDR_X540		0xC820
>-#define IXGBE_TEMP_PROV_2_ADDR_X540		0xC421
>-#define IXGBE_TEMP_PROV_4_ADDR_X540		0xC423
>-#define IXGBE_TEMP_STATUS_PAGE_X540		0x1E
>-#define IXGBE_TEMP_HIGH_FAILURE_BIT_X540	0xE
>-#define IXGBE_TEMP_HIGH_WARNING_BIT_X540	0xC
> 
> /* Manageablility Host Interface defines */
> #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH	1792 /* Num of bytes in range */
> #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH	448 /* Num of dwords in range */
> #define IXGBE_HI_COMMAND_TIMEOUT	500 /* Process HI command limit */
>+#define IXGBE_HI_FLASH_ERASE_TIMEOUT	1000 /* Process Erase command limit */
>+#define IXGBE_HI_FLASH_UPDATE_TIMEOUT	5000 /* Process Update command limit */
>+#define IXGBE_HI_FLASH_APPLY_TIMEOUT	0 /* Process Apply command limit */
> 
> /* CEM Support */
> #define FW_CEM_HDR_LEN			0x4
>@@ -2439,7 +2555,17 @@
> #define FW_CEM_UNUSED_VER		0x0
> #define FW_CEM_MAX_RETRIES		3
> #define FW_CEM_RESP_STATUS_SUCCESS	0x1
>-
>+#define FW_READ_SHADOW_RAM_CMD		0x31
>+#define FW_READ_SHADOW_RAM_LEN		0x6
>+#define FW_WRITE_SHADOW_RAM_CMD		0x33
>+#define FW_WRITE_SHADOW_RAM_LEN		0xA /* 8 plus 1 WORD to write */
>+#define FW_SHADOW_RAM_DUMP_CMD		0x36
>+#define FW_SHADOW_RAM_DUMP_LEN		0
>+#define FW_DEFAULT_CHECKSUM		0xFF /* checksum always 0xFF */
>+#define FW_NVM_DATA_OFFSET		3
>+#define FW_MAX_READ_BUFFER_SIZE		1024
>+#define FW_DISABLE_RXEN_CMD		0xDE
>+#define FW_DISABLE_RXEN_LEN		0x1
> /* Host Interface Command Structures */
> 
> struct ixgbe_hic_hdr {
>@@ -2452,6 +2578,25 @@
> 	u8 checksum;
> };
> 
>+struct ixgbe_hic_hdr2_req {
>+	u8 cmd;
>+	u8 buf_lenh;
>+	u8 buf_lenl;
>+	u8 checksum;
>+};
>+
>+struct ixgbe_hic_hdr2_rsp {
>+	u8 cmd;
>+	u8 buf_lenl;
>+	u8 buf_lenh_status;	/* 7-5: high bits of buf_len, 4-0: status */
>+	u8 checksum;
>+};
>+
>+union ixgbe_hic_hdr2 {
>+	struct ixgbe_hic_hdr2_req req;
>+	struct ixgbe_hic_hdr2_rsp rsp;
>+};
>+
> struct ixgbe_hic_drv_info {
> 	struct ixgbe_hic_hdr hdr;
> 	u8 port_num;
>@@ -2463,6 +2608,33 @@
> 	u16 pad2; /* end spacing to ensure length is mult. of dword2 */
> };
> 
>+/* These need to be dword aligned */
>+struct ixgbe_hic_read_shadow_ram {
>+	union ixgbe_hic_hdr2 hdr;
>+	u32 address;
>+	u16 length;
>+	u16 pad2;
>+	u16 data;
>+	u16 pad3;
>+};
>+
>+struct ixgbe_hic_write_shadow_ram {
>+	union ixgbe_hic_hdr2 hdr;
>+	u32 address;
>+	u16 length;
>+	u16 pad2;
>+	u16 data;
>+	u16 pad3;
>+};
>+
>+struct ixgbe_hic_disable_rxen {
>+	struct ixgbe_hic_hdr hdr;
>+	u8  port_number;
>+	u8  pad2;
>+	u16 pad3;
>+};
>+
>+
> /* Transmit Descriptor - Legacy */
> struct ixgbe_legacy_tx_desc {
> 	u64 buffer_addr; /* Address of the descriptor's data buffer */
>@@ -2611,6 +2783,8 @@
> #define IXGBE_LINK_SPEED_UNKNOWN	0
> #define IXGBE_LINK_SPEED_100_FULL	0x0008
> #define IXGBE_LINK_SPEED_1GB_FULL	0x0020
>+#define IXGBE_LINK_SPEED_2_5GB_FULL	0x0400
>+#define IXGBE_LINK_SPEED_5GB_FULL	0x0800
> #define IXGBE_LINK_SPEED_10GB_FULL	0x0080
> #define IXGBE_LINK_SPEED_82598_AUTONEG	(IXGBE_LINK_SPEED_1GB_FULL | \
> 					 IXGBE_LINK_SPEED_10GB_FULL)
>@@ -2710,6 +2884,7 @@
> #define IXGBE_ATR_L4TYPE_TCP		0x2
> #define IXGBE_ATR_L4TYPE_SCTP		0x3
> #define IXGBE_ATR_L4TYPE_IPV6_MASK	0x4
>+#define IXGBE_ATR_L4TYPE_TUNNEL_MASK	0x10
> enum ixgbe_atr_flow_type {
> 	IXGBE_ATR_FLOW_TYPE_IPV4	= 0x0,
> 	IXGBE_ATR_FLOW_TYPE_UDPV4	= 0x1,
>@@ -2719,6 +2894,14 @@
> 	IXGBE_ATR_FLOW_TYPE_UDPV6	= 0x5,
> 	IXGBE_ATR_FLOW_TYPE_TCPV6	= 0x6,
> 	IXGBE_ATR_FLOW_TYPE_SCTPV6	= 0x7,
>+	IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4	= 0x10,
>+	IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4	= 0x11,
>+	IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4	= 0x12,
>+	IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4	= 0x13,
>+	IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6	= 0x14,
>+	IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6	= 0x15,
>+	IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6	= 0x16,
>+	IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6	= 0x17,
> };
> 
> /* Flow Director ATR input struct. */
>@@ -2730,6 +2913,9 @@
> 	 * flow_type	- 1 byte
> 	 * vlan_id	- 2 bytes
> 	 * src_ip	- 16 bytes
>+	 * inner_mac	- 6 bytes
>+	 * cloud_mode	- 2 bytes
>+	 * tni_vni	- 4 bytes
> 	 * dst_ip	- 16 bytes
> 	 * src_port	- 2 bytes
> 	 * dst_port	- 2 bytes
>@@ -2742,12 +2928,15 @@
> 		__be16 vlan_id;
> 		__be32 dst_ip[4];
> 		__be32 src_ip[4];
>+		u8 inner_mac[6];
>+		__be16 tunnel_type;
>+		__be32 tni_vni;
> 		__be16 src_port;
> 		__be16 dst_port;
> 		__be16 flex_bytes;
> 		__be16 bkt_hash;
> 	} formatted;
>-	__be32 dword_stream[11];
>+	__be32 dword_stream[14];
> };
> 
> /* Flow Director compressed ATR hash input struct */
>@@ -2812,6 +3001,10 @@
> 	ixgbe_phy_sfp_ftl_active,
> 	ixgbe_phy_sfp_unknown,
> 	ixgbe_phy_sfp_intel,
>+	ixgbe_phy_qsfp_passive_unknown,
>+	ixgbe_phy_qsfp_active_unknown,
>+	ixgbe_phy_qsfp_intel,
>+	ixgbe_phy_qsfp_unknown,
> 	ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/
> 	ixgbe_phy_generic
> };
>@@ -2851,6 +3044,7 @@
> 	ixgbe_media_type_unknown = 0,
> 	ixgbe_media_type_fiber,
> 	ixgbe_media_type_fiber_fixed,
>+	ixgbe_media_type_fiber_qsfp,
> 	ixgbe_media_type_copper,
> 	ixgbe_media_type_backplane,
> 	ixgbe_media_type_cx4,
>@@ -2880,6 +3074,7 @@
> 	ixgbe_bus_type_pci,
> 	ixgbe_bus_type_pcix,
> 	ixgbe_bus_type_pci_express,
>+	ixgbe_bus_type_internal,
> 	ixgbe_bus_type_reserved
> };
> 
>@@ -3036,7 +3231,7 @@
> 	s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
> 	s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
> 	s32 (*update_checksum)(struct ixgbe_hw *);
>-	u16 (*calc_checksum)(struct ixgbe_hw *);
>+	s32 (*calc_checksum)(struct ixgbe_hw *);
> };
> 
> struct ixgbe_mac_operations {
>@@ -3062,8 +3257,10 @@
> 	s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
> 	s32 (*disable_sec_rx_path)(struct ixgbe_hw *);
> 	s32 (*enable_sec_rx_path)(struct ixgbe_hw *);
>-	s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
>-	void (*release_swfw_sync)(struct ixgbe_hw *, u16);
>+	s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32);
>+	void (*release_swfw_sync)(struct ixgbe_hw *, u32);
>+	s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);
>+	s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);
> 
> 	/* Link */
> 	void (*disable_tx_laser)(struct ixgbe_hw *);
>@@ -3114,6 +3311,12 @@
> 	s32 (*dmac_update_tcs)(struct ixgbe_hw *hw);
> 	s32 (*dmac_config_tcs)(struct ixgbe_hw *hw);
> 	void (*get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map);
>+	s32 (*setup_eee)(struct ixgbe_hw *hw, bool enable_eee);
>+	void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int);
>+	void (*set_source_address_pruning)(struct ixgbe_hw *, bool,
>+					   unsigned int);
>+	void (*disable_rx)(struct ixgbe_hw *hw);
>+	void (*enable_rx)(struct ixgbe_hw *hw);
> };
> 
> struct ixgbe_phy_operations {
>@@ -3126,6 +3329,7 @@
> 	s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *);
> 	s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16);
> 	s32 (*setup_link)(struct ixgbe_hw *);
>+	s32 (*setup_internal_link)(struct ixgbe_hw *);
> 	s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
> 	s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
> 	s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
>@@ -3135,6 +3339,8 @@
> 	s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
> 	s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
> 	void (*i2c_bus_clear)(struct ixgbe_hw *);
>+	s32 (*read_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);
>+	s32 (*write_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);
> 	s32 (*check_overtemp)(struct ixgbe_hw *);
> };
> 
>@@ -3169,7 +3375,6 @@
> 	u32 max_tx_queues;
> 	u32 max_rx_queues;
> 	u32 orig_autoc;
>-	u32 cached_autoc;
> 	u8  san_mac_rar_index;
> 	bool get_link_status;
> 	u32 orig_autoc2;
>@@ -3178,6 +3383,7 @@
> 	bool orig_link_settings_stored;
> 	bool autotry_restart;
> 	u8 flags;
>+	bool set_lben;
> };
> 
> struct ixgbe_phy_info {
>@@ -3189,6 +3395,7 @@
> 	bool sfp_setup_needed;
> 	u32 revision;
> 	enum ixgbe_media_type media_type;
>+	u32 phy_semaphore_mask;
> 	bool reset_disable;
> 	ixgbe_autoneg_advertised autoneg_advertised;
> 	enum ixgbe_smart_speed smart_speed;
>@@ -3195,6 +3402,7 @@
> 	bool smart_speed_active;
> 	bool multispeed_fiber;
> 	bool reset_if_overtemp;
>+	bool qsfp_shared_i2c_bus;
> };
> 
> #include "ixgbe_mbx.h"
>@@ -3229,7 +3437,7 @@
> };
> 
> struct ixgbe_hw {
>-	u8 *hw_addr;
>+	u8 IOMEM *hw_addr;
> 	void *back;
> 	struct ixgbe_mac_info mac;
> 	struct ixgbe_addr_filter_info addr_ctrl;
>@@ -3247,7 +3455,6 @@
> 	int api_version;
> 	bool force_full_reset;
> 	bool allow_unsupported_sfp;
>-	bool mng_fw_enabled;
> 	bool wol_enabled;
> };
> 
>@@ -3292,7 +3499,9 @@
> #define IXGBE_ERR_OUT_OF_MEM			-34
> #define IXGBE_ERR_FEATURE_NOT_SUPPORTED		-36
> #define IXGBE_ERR_EEPROM_PROTECTED_REGION	-37
>+#define IXGBE_ERR_FDIR_CMD_INCOMPLETE		-38
> 
> #define IXGBE_NOT_IMPLEMENTED			0x7FFFFFFF
> 
>+
> #endif /* _IXGBE_TYPE_H_ */
>Index: ixgbe_vf.c
>===================================================================
>--- ixgbe_vf.c	(revision 273551)
>+++ ixgbe_vf.c	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>@@ -89,6 +89,49 @@
> 	return IXGBE_SUCCESS;
> }
> 
>+/* ixgbe_virt_clr_reg - Set register to default (power on) state.
>+ *  @hw: pointer to hardware structure
>+ */
>+static void ixgbe_virt_clr_reg(struct ixgbe_hw *hw)
>+{
>+	int i;
>+	u32 vfsrrctl;
>+	u32 vfdca_rxctrl;
>+	u32 vfdca_txctrl;
>+
>+	/* VRSRRCTL default values (BSIZEPACKET = 2048, BSIZEHEADER = 256) */
>+	vfsrrctl = 0x100 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
>+	vfsrrctl |= 0x800 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
>+
>+	/* DCA_RXCTRL default value */
>+	vfdca_rxctrl = IXGBE_DCA_RXCTRL_DESC_RRO_EN |
>+		       IXGBE_DCA_RXCTRL_DATA_WRO_EN |
>+		       IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
>+
>+	/* DCA_TXCTRL default value */
>+	vfdca_txctrl = IXGBE_DCA_TXCTRL_DESC_RRO_EN |
>+		       IXGBE_DCA_TXCTRL_DESC_WRO_EN |
>+		       IXGBE_DCA_TXCTRL_DATA_RRO_EN;
>+
>+	IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0);
>+
>+	for (i = 0; i < 7; i++) {
>+		IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
>+		IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
>+		IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), 0);
>+		IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), vfsrrctl);
>+		IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
>+		IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
>+		IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), 0);
>+		IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAH(i), 0);
>+		IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAL(i), 0);
>+		IXGBE_WRITE_REG(hw, IXGBE_VFDCA_RXCTRL(i), vfdca_rxctrl);
>+		IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i), vfdca_txctrl);
>+	}
>+
>+	IXGBE_WRITE_FLUSH(hw);
>+}
>+
> /**
>  *  ixgbe_start_hw_vf - Prepare hardware for Tx/Rx
>  *  @hw: pointer to hardware structure
>@@ -134,7 +177,7 @@
> 	struct ixgbe_mbx_info *mbx = &hw->mbx;
> 	u32 timeout = IXGBE_VF_INIT_TIMEOUT;
> 	s32 ret_val = IXGBE_ERR_INVALID_MAC_ADDR;
>-	u32 ctrl, msgbuf[IXGBE_VF_PERMADDR_MSG_LEN];
>+	u32 msgbuf[IXGBE_VF_PERMADDR_MSG_LEN];
> 	u8 *addr = (u8 *)(&msgbuf[1]);
> 
> 	DEBUGFUNC("ixgbevf_reset_hw_vf");
>@@ -145,8 +188,7 @@
> 
> 	DEBUGOUT("Issuing a function level reset to MAC\n");
> 
>-	ctrl = IXGBE_VFREAD_REG(hw, IXGBE_VFCTRL) | IXGBE_CTRL_RST;
>-	IXGBE_VFWRITE_REG(hw, IXGBE_VFCTRL, ctrl);
>+	IXGBE_VFWRITE_REG(hw, IXGBE_VFCTRL, IXGBE_CTRL_RST);
> 	IXGBE_WRITE_FLUSH(hw);
> 
> 	msec_delay(50);
>@@ -160,6 +202,9 @@
> 	if (!timeout)
> 		return IXGBE_ERR_RESET_FAILED;
> 
>+	/* Reset VF registers to initial values */
>+	ixgbe_virt_clr_reg(hw);
>+
> 	/* mailbox timeout can now become active */
> 	mbx->timeout = IXGBE_VF_MBX_INIT_TIMEOUT;
> 
>@@ -224,6 +269,8 @@
> 		reg_val &= ~IXGBE_RXDCTL_ENABLE;
> 		IXGBE_VFWRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val);
> 	}
>+	/* Clear packet split and pool config */
>+	IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0);
> 
> 	/* flush all queues disables */
> 	IXGBE_WRITE_FLUSH(hw);
>@@ -512,6 +559,21 @@
> 	if (!(links_reg & IXGBE_LINKS_UP))
> 		goto out;
> 
>+	/* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
>+	 * before the link status is correct
>+	 */
>+	if (mac->type == ixgbe_mac_82599_vf) {
>+		int i;
>+
>+		for (i = 0; i < 5; i++) {
>+			usec_delay(100);
>+			links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
>+
>+			if (!(links_reg & IXGBE_LINKS_UP))
>+				goto out;
>+		}
>+	}
>+
> 	switch (links_reg & IXGBE_LINKS_SPEED_82599) {
> 	case IXGBE_LINKS_SPEED_10G_82599:
> 		*speed = IXGBE_LINK_SPEED_10GB_FULL;
>Index: ixgbe_vf.h
>===================================================================
>--- ixgbe_vf.h	(revision 273551)
>+++ ixgbe_vf.h	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>Index: ixgbe_x540.c
>===================================================================
>--- ixgbe_x540.c	(revision 273551)
>+++ ixgbe_x540.c	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>@@ -38,6 +38,13 @@
> #include "ixgbe_common.h"
> #include "ixgbe_phy.h"
> 
>+#define IXGBE_X540_MAX_TX_QUEUES	128
>+#define IXGBE_X540_MAX_RX_QUEUES	128
>+#define IXGBE_X540_RAR_ENTRIES		128
>+#define IXGBE_X540_MC_TBL_SIZE		128
>+#define IXGBE_X540_VFT_TBL_SIZE		128
>+#define IXGBE_X540_RX_PB_SIZE		384
>+
> static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
> static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
> static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
>@@ -116,12 +123,12 @@
> 	mac->ops.check_link = &ixgbe_check_mac_link_generic;
> 
> 
>-	mac->mcft_size		= 128;
>-	mac->vft_size		= 128;
>-	mac->num_rar_entries	= 128;
>-	mac->rx_pb_size		= 384;
>-	mac->max_tx_queues	= 128;
>-	mac->max_rx_queues	= 128;
>+	mac->mcft_size		= IXGBE_X540_MC_TBL_SIZE;
>+	mac->vft_size		= IXGBE_X540_VFT_TBL_SIZE;
>+	mac->num_rar_entries	= IXGBE_X540_RAR_ENTRIES;
>+	mac->rx_pb_size		= IXGBE_X540_RX_PB_SIZE;
>+	mac->max_rx_queues	= IXGBE_X540_MAX_RX_QUEUES;
>+	mac->max_tx_queues	= IXGBE_X540_MAX_TX_QUEUES;
> 	mac->max_msix_vectors	= ixgbe_get_pcie_msix_count_generic(hw);
> 
> 	/*
>@@ -469,18 +476,20 @@
>  *  be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
>  *
>  *  @hw: pointer to hardware structure
>+ *
>+ *  Returns a negative error code on error, or the 16-bit checksum
>  **/
>-u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
>+s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
> {
>-	u16 i;
>-	u16 j;
>+	u16 i, j;
> 	u16 checksum = 0;
> 	u16 length = 0;
> 	u16 pointer = 0;
> 	u16 word = 0;
>+	u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
>+	u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
> 
>-	/*
>-	 * Do not use hw->eeprom.ops.read because we do not want to take
>+	/* Do not use hw->eeprom.ops.read because we do not want to take
> 	 * the synchronization semaphores here. Instead use
> 	 * ixgbe_read_eerd_generic
> 	 */
>@@ -488,25 +497,25 @@
> 	DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
> 
> 	/* Include 0x0-0x3F in the checksum */
>-	for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
>-		if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
>+	for (i = 0; i <= checksum_last_word; i++) {
>+		if (ixgbe_read_eerd_generic(hw, i, &word)) {
> 			DEBUGOUT("EEPROM read failed\n");
>-			break;
>+			return IXGBE_ERR_EEPROM;
> 		}
>-		checksum += word;
>+		if (i != IXGBE_EEPROM_CHECKSUM)
>+			checksum += word;
> 	}
> 
>-	/*
>-	 * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
>+	/* Include all data from pointers 0x3, 0x6-0xE.  This excludes the
> 	 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
> 	 */
>-	for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
>+	for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
> 		if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
> 			continue;
> 
>-		if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
>+		if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
> 			DEBUGOUT("EEPROM read failed\n");
>-			break;
>+			return IXGBE_ERR_EEPROM;
> 		}
> 
> 		/* Skip pointer section if the pointer is invalid. */
>@@ -514,10 +523,9 @@
> 		    pointer >= hw->eeprom.word_size)
> 			continue;
> 
>-		if (ixgbe_read_eerd_generic(hw, pointer, &length) !=
>-		    IXGBE_SUCCESS) {
>+		if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
> 			DEBUGOUT("EEPROM read failed\n");
>-			break;
>+			return IXGBE_ERR_EEPROM;
> 		}
> 
> 		/* Skip pointer section if length is invalid. */
>@@ -525,11 +533,10 @@
> 		    (pointer + length) >= hw->eeprom.word_size)
> 			continue;
> 
>-		for (j = pointer+1; j <= pointer+length; j++) {
>-			if (ixgbe_read_eerd_generic(hw, j, &word) !=
>-			    IXGBE_SUCCESS) {
>+		for (j = pointer + 1; j <= pointer + length; j++) {
>+			if (ixgbe_read_eerd_generic(hw, j, &word)) {
> 				DEBUGOUT("EEPROM read failed\n");
>-				break;
>+				return IXGBE_ERR_EEPROM;
> 			}
> 			checksum += word;
> 		}
>@@ -537,7 +544,7 @@
> 
> 	checksum = (u16)IXGBE_EEPROM_SUM - checksum;
> 
>-	return checksum;
>+	return (s32)checksum;
> }
> 
> /**
>@@ -557,48 +564,49 @@
> 
> 	DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
> 
>-	/*
>-	 * Read the first word from the EEPROM. If this times out or fails, do
>+	/* Read the first word from the EEPROM. If this times out or fails, do
> 	 * not continue or we could be in for a very long wait while every
> 	 * EEPROM read fails
> 	 */
> 	status = hw->eeprom.ops.read(hw, 0, &checksum);
>-
>-	if (status != IXGBE_SUCCESS) {
>+	if (status) {
> 		DEBUGOUT("EEPROM read failed\n");
>-		goto out;
>+		return status;
> 	}
> 
>-	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
>-	    IXGBE_SUCCESS) {
>-		checksum = hw->eeprom.ops.calc_checksum(hw);
>+	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
>+		return IXGBE_ERR_SWFW_SYNC;
> 
>-		/*
>-		 * Do not use hw->eeprom.ops.read because we do not want to take
>-		 * the synchronization semaphores twice here.
>-		*/
>-		ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
>-					&read_checksum);
>+	status = hw->eeprom.ops.calc_checksum(hw);
>+	if (status < 0)
>+		goto out;
> 
>-		/*
>-		 * Verify read checksum from EEPROM is the same as
>-		 * calculated checksum
>-		 */
>-		if (read_checksum != checksum) {
>-			status = IXGBE_ERR_EEPROM_CHECKSUM;
>-			ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
>-				     "Invalid EEPROM checksum");
>-		}
>+	checksum = (u16)(status & 0xffff);
> 
>-		/* If the user cares, return the calculated checksum */
>-		if (checksum_val)
>-			*checksum_val = checksum;
>-		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
>-	} else {
>-		status = IXGBE_ERR_SWFW_SYNC;
>+	/* Do not use hw->eeprom.ops.read because we do not want to take
>+	 * the synchronization semaphores twice here.
>+	 */
>+	status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
>+					 &read_checksum);
>+	if (status)
>+		goto out;
>+
>+	/* Verify read checksum from EEPROM is the same as
>+	 * calculated checksum
>+	 */
>+	if (read_checksum != checksum) {
>+		ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
>+			     "Invalid EEPROM checksum");
>+		status = IXGBE_ERR_EEPROM_CHECKSUM;
> 	}
> 
>+	/* If the user cares, return the calculated checksum */
>+	if (checksum_val)
>+		*checksum_val = checksum;
>+
> out:
>+	hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
>+
> 	return status;
> }
> 
>@@ -617,34 +625,37 @@
> 
> 	DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
> 
>-	/*
>-	 * Read the first word from the EEPROM. If this times out or fails, do
>+	/* Read the first word from the EEPROM. If this times out or fails, do
> 	 * not continue or we could be in for a very long wait while every
> 	 * EEPROM read fails
> 	 */
> 	status = hw->eeprom.ops.read(hw, 0, &checksum);
>-
>-	if (status != IXGBE_SUCCESS)
>+	if (status) {
> 		DEBUGOUT("EEPROM read failed\n");
>+		return status;
>+	}
> 
>-	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
>-	    IXGBE_SUCCESS) {
>-		checksum = hw->eeprom.ops.calc_checksum(hw);
>+	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
>+		return IXGBE_ERR_SWFW_SYNC;
> 
>-		/*
>-		 * Do not use hw->eeprom.ops.write because we do not want to
>-		 * take the synchronization semaphores twice here.
>-		*/
>-		status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
>-						  checksum);
>+	status = hw->eeprom.ops.calc_checksum(hw);
>+	if (status < 0)
>+		goto out;
> 
>-		if (status == IXGBE_SUCCESS)
>-			status = ixgbe_update_flash_X540(hw);
>-		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
>-	} else {
>-		status = IXGBE_ERR_SWFW_SYNC;
>-	}
>+	checksum = (u16)(status & 0xffff);
> 
>+	/* Do not use hw->eeprom.ops.write because we do not want to
>+	 * take the synchronization semaphores twice here.
>+	 */
>+	status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
>+	if (status)
>+		goto out;
>+
>+	status = ixgbe_update_flash_X540(hw);
>+
>+out:
>+	hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
>+
> 	return status;
> }
> 
>@@ -658,7 +669,7 @@
> s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
> {
> 	u32 flup;
>-	s32 status = IXGBE_ERR_EEPROM;
>+	s32 status;
> 
> 	DEBUGFUNC("ixgbe_update_flash_X540");
> 
>@@ -716,7 +727,7 @@
> 			status = IXGBE_SUCCESS;
> 			break;
> 		}
>-		usec_delay(5);
>+		msec_delay(5);
> 	}
> 
> 	if (i == IXGBE_FLUDONE_ATTEMPTS)
>@@ -734,34 +745,30 @@
>  *  Acquires the SWFW semaphore thought the SW_FW_SYNC register for
>  *  the specified function (CSR, PHY0, PHY1, NVM, Flash)
>  **/
>-s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
>+s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
> {
>+	u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
>+	u32 fwmask = swmask << 5;
>+	u32 timeout = 200;
>+	u32 hwmask = 0;
> 	u32 swfw_sync;
>-	u32 swmask = mask;
>-	u32 fwmask = mask << 5;
>-	u32 hwmask = 0;
>-	u32 timeout = 200;
> 	u32 i;
>-	s32 ret_val = IXGBE_SUCCESS;
> 
> 	DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
> 
>-	if (swmask == IXGBE_GSSR_EEP_SM)
>-		hwmask = IXGBE_GSSR_FLASH_SM;
>+	if (swmask & IXGBE_GSSR_EEP_SM)
>+		hwmask |= IXGBE_GSSR_FLASH_SM;
> 
> 	/* SW only mask doesn't have FW bit pair */
>-	if (swmask == IXGBE_GSSR_SW_MNG_SM)
>-		fwmask = 0;
>+	if (mask & IXGBE_GSSR_SW_MNG_SM)
>+		swmask |= IXGBE_GSSR_SW_MNG_SM;
> 
> 	for (i = 0; i < timeout; i++) {
>-		/*
>-		 * SW NVM semaphore bit is used for access to all
>+		/* SW NVM semaphore bit is used for access to all
> 		 * SW_FW_SYNC bits (not just NVM)
> 		 */
>-		if (ixgbe_get_swfw_sync_semaphore(hw)) {
>-			ret_val = IXGBE_ERR_SWFW_SYNC;
>-			goto out;
>-		}
>+		if (ixgbe_get_swfw_sync_semaphore(hw))
>+			return IXGBE_ERR_SWFW_SYNC;
> 
> 		swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
> 		if (!(swfw_sync & (fwmask | swmask | hwmask))) {
>@@ -768,24 +775,22 @@
> 			swfw_sync |= swmask;
> 			IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
> 			ixgbe_release_swfw_sync_semaphore(hw);
>-			goto out;
>-		} else {
>-			/*
>-			 * Firmware currently using resource (fwmask), hardware
>-			 * currently using resource (hwmask), or other software
>-			 * thread currently using resource (swmask)
>-			 */
>-			ixgbe_release_swfw_sync_semaphore(hw);
> 			msec_delay(5);
>+			return IXGBE_SUCCESS;
> 		}
>+		/* Firmware currently using resource (fwmask), hardware
>+		 * currently using resource (hwmask), or other software
>+		 * thread currently using resource (swmask)
>+		 */
>+		ixgbe_release_swfw_sync_semaphore(hw);
>+		msec_delay(5);
> 	}
> 
> 	/* Failed to get SW only semaphore */
> 	if (swmask == IXGBE_GSSR_SW_MNG_SM) {
>-		ret_val = IXGBE_ERR_SWFW_SYNC;
> 		ERROR_REPORT1(IXGBE_ERROR_POLLING,
> 			     "Failed to get SW only semaphore");
>-		goto out;
>+		return IXGBE_ERR_SWFW_SYNC;
> 	}
> 
> 	/* If the resource is not released by the FW/HW the SW can assume that
>@@ -793,17 +798,15 @@
> 	 * of the requested resource(s) while ignoring the corresponding FW/HW
> 	 * bits in the SW_FW_SYNC register.
> 	 */
>+	if (ixgbe_get_swfw_sync_semaphore(hw))
>+		return IXGBE_ERR_SWFW_SYNC;
> 	swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
> 	if (swfw_sync & (fwmask | hwmask)) {
>-		if (ixgbe_get_swfw_sync_semaphore(hw)) {
>-			ret_val = IXGBE_ERR_SWFW_SYNC;
>-			goto out;
>-		}
>-
> 		swfw_sync |= swmask;
> 		IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
> 		ixgbe_release_swfw_sync_semaphore(hw);
> 		msec_delay(5);
>+		return IXGBE_SUCCESS;
> 	}
> 	/* If the resource is not released by other SW the SW can assume that
> 	 * the other SW malfunctions. In that case the SW should clear all SW
>@@ -810,15 +813,17 @@
> 	 * flags that it does not own and then repeat the whole process once
> 	 * again.
> 	 */
>-	else if (swfw_sync & swmask) {
>-		ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM |
>-			IXGBE_GSSR_PHY0_SM | IXGBE_GSSR_PHY1_SM |
>-			IXGBE_GSSR_MAC_CSR_SM);
>-		ret_val = IXGBE_ERR_SWFW_SYNC;
>+	if (swfw_sync & swmask) {
>+		u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
>+			    IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM;
>+
>+		ixgbe_release_swfw_sync_X540(hw, rmask);
>+		ixgbe_release_swfw_sync_semaphore(hw);
>+		return IXGBE_ERR_SWFW_SYNC;
> 	}
>+	ixgbe_release_swfw_sync_semaphore(hw);
> 
>-out:
>-	return ret_val;
>+	return IXGBE_ERR_SWFW_SYNC;
> }
> 
> /**
>@@ -829,10 +834,10 @@
>  *  Releases the SWFW semaphore through the SW_FW_SYNC register
>  *  for the specified function (CSR, PHY0, PHY1, EVM, Flash)
>  **/
>-void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
>+void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
> {
>+	u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
> 	u32 swfw_sync;
>-	u32 swmask = mask;
> 
> 	DEBUGFUNC("ixgbe_release_swfw_sync_X540");
> 
>@@ -843,10 +848,11 @@
> 	IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
> 
> 	ixgbe_release_swfw_sync_semaphore(hw);
>+	msec_delay(5);
> }
> 
> /**
>- *  ixgbe_get_nvm_semaphore - Get hardware semaphore
>+ *  ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
>  *  @hw: pointer to hardware structure
>  *
>  *  Sets the hardware semaphores so SW/FW can gain control of shared resources
>@@ -904,7 +910,7 @@
> }
> 
> /**
>- *  ixgbe_release_nvm_semaphore - Release hardware semaphore
>+ *  ixgbe_release_swfw_sync_semaphore - Release hardware semaphore
>  *  @hw: pointer to hardware structure
>  *
>  *  This function clears hardware semaphore bits.
>Index: ixgbe_x540.h
>===================================================================
>--- ixgbe_x540.h	(revision 273551)
>+++ ixgbe_x540.h	(working copy)
>@@ -1,6 +1,6 @@
> /******************************************************************************
> 
>-  Copyright (c) 2001-2013, Intel Corporation 
>+  Copyright (c) 2001-2014, Intel Corporation 
>   All rights reserved.
>   
>   Redistribution and use in source and binary forms, with or without 
>@@ -55,11 +55,11 @@
> 				 u16 *data);
> s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw);
> s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, u16 *checksum_val);
>-u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw);
>+s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw);
> s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
> 
>-s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
>-void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
>+s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask);
>+void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask);
> 
> s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index);
> s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index);

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Attachments on bug 194234: 148084 | 148085 | 148597 | 148598