Attachment 159354 Details for Bug 201958 – rt5350 support

[patch] rt5350 support

rt5350.diff (text/plain), 29.93 KB, created by Emmanuel Vadot on 2015-07-29 05:07:57 UTC

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Creator: Emmanuel Vadot

Created: 2015-07-29 05:07:57 UTC

Size: 29.93 KB

patch

obsolete

>diff --git a/sys/conf/options.mips b/sys/conf/options.mips
>index 93d4ed3..3ec2d0a 100644
>--- a/sys/conf/options.mips
>+++ b/sys/conf/options.mips
>@@ -113,6 +113,13 @@ AR71XX_ENV_ROUTERBOOT		opt_ar71xx.h
> AR71XX_ATH_EEPROM		opt_ar71xx.h
> 
> #
>+# Options that choose the Ralink RT model
>+#
>+RT3050F				opt_global.h
>+RT3052F				opt_global.h
>+RT5350F				opt_global.h
>+
>+#
> # Options that control the Ralink RT305xF Etherenet MAC.
> #
> IF_RT_DEBUG			opt_if_rt.h
>diff --git a/sys/mips/conf/OLIMEX_RT5350.hints b/sys/mips/conf/OLIMEX_RT5350.hints
>new file mode 100644
>index 0000000..040e8bb
>--- /dev/null
>+++ b/sys/mips/conf/OLIMEX_RT5350.hints
>@@ -0,0 +1,40 @@
>+# $FreeBSD$
>+# device.hints
>+hint.obio.0.at="nexus0"
>+hint.obio.0.maddr=0x10000000
>+hint.obio.0.msize=0x10000000
>+
>+hint.nvram.0.sig=0xe5e60a74
>+hint.nvram.0.base=0x1f030000
>+hint.nvram.0.maxsize=0x2000
>+hint.nvram.0.flags=3 # 1 = No check, 2 = Format Generic
>+hint.nvram.1.sig=0x5a045e94
>+hint.nvram.1.base=0x1f032000
>+hint.nvram.1.maxsize=0x4000
>+hint.nvram.1.flags=3 # 1 = No check, 2 = Format Generic
>+
>+# on-board Ralink Frame Engine
>+hint.rt.0.at="nexus0"
>+hint.rt.0.maddr=0x10100000
>+hint.rt.0.msize=0x10000
>+hint.rt.0.irq=3
>+# macaddr can be statically set
>+#hint.rt.0.macaddr="xx:xx:xx:xx:xx:xx"
>+
>+# Settings for OLIMEX RT5350F-EVB
>+# Setups button as input in GPIO0, relays as output on GPIO12 and GPIO14
>+hint.gpio.0.function_set=0x1C
>+hint.gpio.0.pinmask=0x5001
>+hint.gpio.0.pinon=0x5000
>+hint.gpio.0.pinin=0x1
>+
>+# on-board Ralink 2872 802.11n core
>+hint.rt2860.0.at="nexus0"
>+hint.rt2860.0.maddr=0x10180000
>+hint.rt2860.0.msize=0x40000
>+hint.rt2860.0.irq=4
>+
>+hint.rt.0.phymask=0x1f
>+hint.rt.0.media=100
>+hint.rt.0.fduplex=1
>+
>diff --git a/sys/mips/conf/OLIMEX_RT5350_MFS b/sys/mips/conf/OLIMEX_RT5350_MFS
>new file mode 100644
>index 0000000..b1be900
>--- /dev/null
>+++ b/sys/mips/conf/OLIMEX_RT5350_MFS
>@@ -0,0 +1,16 @@
>+#
>+# OLIMEX RT5350F: Boot from TFTP
>+#
>+
>+include		"RT5350_BASE"
>+ident		"OLIMEX_RT5350"
>+hints		"OLIMEX_RT5350.hints"
>+
>+device		md
>+device          geom_uzip
>+options         GEOM_UZIP
>+
>+options         ROOTDEVNAME=\"ufs:md0.uzip\"
>+
>+options         MD_ROOT
>+options         MD_ROOT_SIZE=6144
>diff --git a/sys/mips/conf/RT5350_BASE b/sys/mips/conf/RT5350_BASE
>new file mode 100644
>index 0000000..0620b3d
>--- /dev/null
>+++ b/sys/mips/conf/RT5350_BASE
>@@ -0,0 +1,105 @@
>+# RT305X -- Kernel configuration file for FreeBSD/mips for Ralink RT305xF systems
>+#
>+# For more information on this file, please read the handbook section on
>+# Kernel Configuration Files:
>+#
>+#    http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
>+#
>+# The handbook is also available locally in /usr/share/doc/handbook
>+# if you've installed the doc distribution, otherwise always see the
>+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
>+# latest information.
>+#
>+# An exhaustive list of options and more detailed explanations of the
>+# device lines is also present in the ../../conf/NOTES and NOTES files. 
>+# If you are in doubt as to the purpose or necessity of a line, check first 
>+# in NOTES.
>+#
>+# $FreeBSD$
>+
>+ident		RT5350
>+
>+machine		mips mipsel
>+makeoptions	MIPS_LITTLE_ENDIAN=defined
>+makeoptions	KERNLOADADDR=0x80800000
>+
>+# Don't build any modules yet.
>+makeoptions	MODULES_OVERRIDE="wlan_xauth wlan_wep wlan_tkip wlan_acl wlan_amrr wlan_ccmp wlan_rssadapt if_bridge bridgestp msdosfs md ipfw dummynet libalias geom/geom_label ufs usb/uplcom usb/u3g usb/umodem usb/umass usb/ucom cam zlib"
>+makeoptions	RT5350F
>+
>+include		"../rt305x/std.rt5350"
>+
>+hints		"RT5350_BASE.hints"		#Default places to look for devices.
>+
>+#makeoptions	DEBUG=-g		#Build kernel with gdb(1) debug symbols
>+
>+# Debugging for use in -current
>+#options 	DEADLKRES		#Enable the deadlock resolver
>+#options 	INVARIANTS		#Enable calls of extra sanity checking
>+#options 	INVARIANT_SUPPORT	#Extra sanity checks of internal structures, required by INVARIANTS
>+#options 	WITNESS			#Enable checks to detect deadlocks and cycles
>+#options 	WITNESS_SKIPSPIN	#Don't run witness on spinlocks for speed
>+#options         DIAGNOSTIC
>+#options     DEBUG_LOCKS
>+#options     DEBUG_VFS_LOCKS
>+#options 	GDB
>+options 	DDB
>+options 	KDB
>+
>+options 	SCHED_ULE
>+options 	INET			#InterNETworking
>+options 	NFSCL			#Network Filesystem Client
>+options 	NFS_ROOT		#NFS usable as /, requires NFSCL
>+options 	PSEUDOFS		#Pseudo-filesystem framework
>+#options 	_KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
>+
>+options 	TMPFS			# TMP Memory Filesystem
>+
>+options 	FFS			#Berkeley Fast Filesystem
>+
>+# Options for making kernel less hangry
>+makeoptions	INLINE_LIMIT=1024
>+options 	MAXUSERS=3
>+options 	MAXFILES=512
>+options 	NSFBUFS=256
>+options 	SHMALL=128
>+options 	MSGBUF_SIZE=65536
>+
>+# Options for making kernel smallest 
>+options 	NO_SYSCTL_DESCR		# No description string of sysctl
>+#options 	NO_FFS_SNAPSHOT		# Disable Snapshot supporting
>+options 	SCSI_NO_SENSE_STRINGS
>+options 	SCSI_NO_OP_STRINGS
>+options 	RWLOCK_NOINLINE
>+options 	SX_NOINLINE
>+options 	NO_SWAPPING
>+options         MROUTING                # Multicast routing
>+options 	IPFIREWALL_DEFAULT_TO_ACCEPT
>+
>+device		random
>+device		loop
>+# RT3050F, RT3052F have only pseudo PHYs, so mii not required
>+device		rt
>+
>+device		ether
>+device 		bpf			# Berkeley packet filter
>+device		vlan
>+#device		lagg
>+#device          if_bridge
>+device		uart
>+nodevice	uart_ns8250
>+device 		tun			# Packet tunnel.
>+
>+device		wlan
>+
>+device		gpio
>+device		gpioled
>+
>+device		nvram2env
>+
>+device		usb
>+options 	SCSI_DELAY=1000		# Delay (in ms) before probing SCSI
>+
>+#options 	USB_EHCI_BIG_ENDIAN_DESC        # handle big-endian byte order
>+#options 	USB_DEBUG
>+#options 	USB_REQ_DEBUG
>diff --git a/sys/mips/conf/RT5350_BASE.hints b/sys/mips/conf/RT5350_BASE.hints
>new file mode 100644
>index 0000000..a3d24fd
>--- /dev/null
>+++ b/sys/mips/conf/RT5350_BASE.hints
>@@ -0,0 +1,33 @@
>+# $FreeBSD$
>+# device.hints
>+hint.obio.0.at="nexus0"
>+hint.obio.0.maddr=0x10000000
>+hint.obio.0.msize=0x10000000
>+
>+hint.nvram.0.sig=0xe5e60a74
>+hint.nvram.0.base=0x1f030000
>+hint.nvram.0.maxsize=0x2000
>+hint.nvram.0.flags=3 # 1 = No check, 2 = Format Generic
>+hint.nvram.1.sig=0x5a045e94
>+hint.nvram.1.base=0x1f032000
>+hint.nvram.1.maxsize=0x4000
>+hint.nvram.1.flags=3 # 1 = No check, 2 = Format Generic
>+
>+# on-board Ralink Frame Engine
>+hint.rt.0.at="nexus0"
>+hint.rt.0.maddr=0x10100000
>+hint.rt.0.msize=0x10000
>+hint.rt.0.irq=3
>+# macaddr can be statically set
>+#hint.rt.0.macaddr="xx:xx:xx:xx:xx:xx"
>+
>+# on-board Ralink 2872 802.11n core
>+hint.rt2860.0.at="nexus0"
>+hint.rt2860.0.maddr=0x10180000
>+hint.rt2860.0.msize=0x40000
>+hint.rt2860.0.irq=4
>+
>+hint.rt.0.phymask=0x1f
>+hint.rt.0.media=100
>+hint.rt.0.fduplex=1
>+
>diff --git a/sys/mips/rt305x/obio.c b/sys/mips/rt305x/obio.c
>index fd9132a..70046dc 100644
>--- a/sys/mips/rt305x/obio.c
>+++ b/sys/mips/rt305x/obio.c
>@@ -248,9 +248,11 @@ obio_attach(device_t dev)
> 	obio_add_res_child(dev, "uart", 1,
> 	    UARTLITE_BASE, (UARTLITE_END - UARTLITE_BASE + 1),
> 	    IC_UARTLITE);
>+#if defined(RT3050F) || defined(RT3052F)
> 	obio_add_res_child(dev, "cfi", 	0,
> 	    FLASH_BASE, (FLASH_END - FLASH_BASE  + 1),
> 	    -1);
>+#endif
> 	obio_add_res_child(dev, "dotg", 0,
> 	    USB_OTG_BASE, (USB_OTG_END - USB_OTG_BASE  + 1),
> 	    IC_OTG);
>diff --git a/sys/mips/rt305x/rt305x_gpio.c b/sys/mips/rt305x/rt305x_gpio.c
>index 1ce02d7..ecc922b 100644
>--- a/sys/mips/rt305x/rt305x_gpio.c
>+++ b/sys/mips/rt305x/rt305x_gpio.c
>@@ -1,7 +1,8 @@
> /*-
>+ * Copyright (c) 2015, Emmanuel Vadot <manu@bidouilliste.com>
>  * Copyright (c) 2010-2011, Aleksandr Rybalko <ray@ddteam.net>
>  * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
>- * Copyright (c) 2009, Luiz Otavio O Souza. 
>+ * Copyright (c) 2009, Luiz Otavio O Souza.
>  * All rights reserved.
>  *
>  * Redistribution and use in source and binary forms, with or without
>@@ -28,7 +29,7 @@
>  */
> 
> /*
>- * GPIO driver for RT305X SoC.
>+ * GPIO driver for RT305X/RT5350 SoC.
>  */
> 
> #include <sys/cdefs.h>
>@@ -66,7 +67,7 @@ __FBSDID("$FreeBSD$");
> /*
>  * Helpers
>  */
>-static void rt305x_gpio_pin_configure(struct rt305x_gpio_softc *sc, 
>+static void rt305x_gpio_pin_configure(device_t dev, struct rt305x_gpio_softc *sc,
>     struct gpio_pin *pin, uint32_t flags);
> 
> /*
>@@ -97,24 +98,28 @@ static int rt305x_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
> static int rt305x_gpio_pin_toggle(device_t dev, uint32_t pin);
> 
> static void
>-rt305x_gpio_pin_configure(struct rt305x_gpio_softc *sc, struct gpio_pin *pin,
>+rt305x_gpio_pin_configure(device_t dev, struct rt305x_gpio_softc *sc, struct gpio_pin *pin,
>     unsigned int flags)
> {
> 	GPIO_LOCK(sc);
>+	uint32_t reg;
> 
> 	/*
> 	 * Manage input/output
> 	 */
> 	if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
> 		pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
>+		reg = bus_read_4(sc->gpio_mem_res, GPIO_REG(pin->gp_pin, DIR));
> 		if (flags & GPIO_PIN_OUTPUT) {
> 			pin->gp_flags |= GPIO_PIN_OUTPUT;
>-			GPIO_BIT_SET(sc, pin->gp_pin, DIR);
>+			reg |= GPIO_MASK(pin->gp_pin);
> 		}
> 		else {
> 			pin->gp_flags |= GPIO_PIN_INPUT;
>-			GPIO_BIT_CLR(sc, pin->gp_pin, DIR);
>+			reg &= ~GPIO_MASK(pin->gp_pin);
> 		}
>+		bus_write_4(sc->gpio_mem_res, GPIO_REG(pin->gp_pin, DIR), reg);
>+		reg = bus_read_4(sc->gpio_mem_res, GPIO_REG(pin->gp_pin, DIR));
> 	}
> 
> 	if (flags & GPIO_PIN_INVOUT) {
>@@ -141,7 +146,7 @@ rt305x_gpio_pin_configure(struct rt305x_gpio_softc *sc, struct gpio_pin *pin,
> 		pin->gp_flags |= GPIO_PIN_REPORT;
> 		GPIO_BIT_SET(sc, pin->gp_pin, RENA);
> 		GPIO_BIT_SET(sc, pin->gp_pin, FENA);
>-		device_printf(sc->dev, "Will report interrupt on pin %d\n", 
>+		device_printf(sc->dev, "Will report interrupt on pin %d\n",
> 		    pin->gp_pin);
> 
> 	}
>@@ -254,7 +259,7 @@ rt305x_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
> 	if (i >= sc->gpio_npins)
> 		return (EINVAL);
> 
>-	rt305x_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);
>+	rt305x_gpio_pin_configure(dev, sc, &sc->gpio_pins[i], flags);
> 
> 	return (0);
> }
>@@ -275,8 +280,10 @@ rt305x_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
> 
> 
> 	GPIO_LOCK(sc);
>-	if (value) GPIO_BIT_SET(sc, i, DATA);
>-	else       GPIO_BIT_CLR(sc, i, DATA);
>+	if (value)
>+		bus_write_4(sc->gpio_mem_res, GPIO_REG(pin, SET), GPIO_MASK(pin));
>+	else
>+		bus_write_4(sc->gpio_mem_res, GPIO_REG(pin, RESET), GPIO_MASK(pin));
> 	GPIO_UNLOCK(sc);
> 
> 	return (0);
>@@ -287,6 +294,7 @@ rt305x_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
> {
> 	struct rt305x_gpio_softc *sc = device_get_softc(dev);
> 	int i;
>+	uint32_t	data;
> 
> 	for (i = 0; i < sc->gpio_npins; i++) {
> 		if (sc->gpio_pins[i].gp_pin == pin)
>@@ -297,7 +305,9 @@ rt305x_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
> 		return (EINVAL);
> 
> 	GPIO_LOCK(sc);
>-	*val = GPIO_BIT_GET(sc, i, DATA);
>+	data = bus_read_4(sc->gpio_mem_res, GPIO_REG(pin, DATA));
>+	data >>= GPIO_BIT_SHIFT(pin);
>+	*val = data & 1;
> 	GPIO_UNLOCK(sc);
> 
> 	return (0);
>@@ -318,7 +328,7 @@ rt305x_gpio_pin_toggle(device_t dev, uint32_t pin)
> 		return (EINVAL);
> 
> 	GPIO_LOCK(sc);
>-	GPIO_BIT_SET(sc, i, TOG);
>+	bus_write_4(sc->gpio_mem_res, GPIO_REG(pin, TOG), GPIO_MASK(pin));
> 	GPIO_UNLOCK(sc);
> 
> 	return (0);
>@@ -358,7 +368,7 @@ rt305x_gpio_intr(void *arg)
> 			 * if now reset is high, check how long
> 			 * and do reset if less than 2 seconds
> 			 */
>-			if ( reset_pin && 
>+			if ( reset_pin &&
> 			    (time_uptime - sc->reset_gpio_ontime) < 2 )
> 				shutdown_nice(0);
> 
>@@ -375,14 +385,14 @@ rt305x_gpio_intr(void *arg)
> 		if ( (((value & input) >> i) & 1) != sc->gpio_pins[i].gp_last )
> 		{
> 			/* !system=GPIO subsystem=pin7 type=PIN_HIGH period=3 */
>-			snprintf(notify , sizeof(notify ), "period=%d", 
>+			snprintf(notify , sizeof(notify ), "period=%d",
> 			    (uint32_t)time_uptime - sc->gpio_pins[i].gp_time);
> 			snprintf(pinname, sizeof(pinname), "pin%02d", i);
>-			devctl_notify("GPIO", pinname, 
>-			    (((value & input) >> i) & 1)?"PIN_HIGH":"PIN_LOW", 
>+			devctl_notify("GPIO", pinname,
>+			    (((value & input) >> i) & 1)?"PIN_HIGH":"PIN_LOW",
> 			    notify);
>-			printf("GPIO[%s] %s %s\n", pinname, 
>-			    (((value & input) >> i) & 1)?"PIN_HIGH":"PIN_LOW", 
>+			printf("GPIO[%s] %s %s\n", pinname,
>+			    (((value & input) >> i) & 1)?"PIN_HIGH":"PIN_LOW",
> 			    notify);
> 			sc->gpio_pins[i].gp_last = ((value & input) >> i) & 1;
> 			sc->gpio_pins[i].gp_time = time_uptime;
>@@ -402,49 +412,12 @@ rt305x_gpio_probe(device_t dev)
> 	return (0);
> }
> 
>-static uint64_t
>-rt305x_gpio_init(device_t dev)
>-{
>-	uint64_t avl = ~0ULL;
>-	uint32_t gmode = rt305x_sysctl_get(SYSCTL_GPIOMODE);
>-	if (!(gmode & SYSCTL_GPIOMODE_RGMII_GPIO_MODE))
>-		avl &= ~RGMII_GPIO_MODE_MASK;
>-	if (!(gmode & SYSCTL_GPIOMODE_SDRAM_GPIO_MODE))
>-		avl &= ~SDRAM_GPIO_MODE_MASK;
>-	if (!(gmode & SYSCTL_GPIOMODE_MDIO_GPIO_MODE))
>-		avl &= ~MDIO_GPIO_MODE_MASK;
>-	if (!(gmode & SYSCTL_GPIOMODE_JTAG_GPIO_MODE))
>-		avl &= ~JTAG_GPIO_MODE_MASK;
>-	if (!(gmode & SYSCTL_GPIOMODE_UARTL_GPIO_MODE))
>-		avl &= ~UARTL_GPIO_MODE_MASK;
>-	if (!(gmode & SYSCTL_GPIOMODE_SPI_GPIO_MODE))
>-		avl &= ~SPI_GPIO_MODE_MASK;
>-	if (!(gmode & SYSCTL_GPIOMODE_I2C_GPIO_MODE))
>-		avl &= ~I2C_GPIO_MODE_MASK;
>-	if ((gmode & SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO) != 
>-	    SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO)
>-		avl &= ~I2C_GPIO_MODE_MASK;
>-/* D-Link DAP-1350 Board have
>- * MDIO_GPIO_MODE
>- * UARTF_GPIO_MODE
>- * SPI_GPIO_MODE
>- * I2C_GPIO_MODE
>- * So we have 
>- * 00000001 10000000 01111111 11111110
>-*/
>-	return (avl);
>-
>-}
>-
>-#define DAP1350_RESET_GPIO	10
>-
> static int
> rt305x_gpio_attach(device_t dev)
> {
> 	struct rt305x_gpio_softc *sc = device_get_softc(dev);
> 	int i;
>-	uint64_t avlpins = 0;
>-	sc->reset_gpio = DAP1350_RESET_GPIO;
>+	uint32_t reg, mask, pinon, pinin;
> 
> 	KASSERT((device_get_unit(dev) == 0),
> 	    ("rt305x_gpio_gpio: Only one gpio module supported"));
>@@ -462,14 +435,14 @@ rt305x_gpio_attach(device_t dev)
> 		return (ENXIO);
> 	}
> 
>-	if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 
>+	if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
> 	    &sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
> 		device_printf(dev, "unable to allocate IRQ resource\n");
> 		rt305x_gpio_detach(dev);
> 		return (ENXIO);
> 	}
> 
>-	if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC, 
>+	if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,
> 	    /* rt305x_gpio_filter, */
> 	    rt305x_gpio_intr, NULL, sc, &sc->gpio_ih))) {
> 		device_printf(dev,
>@@ -479,36 +452,73 @@ rt305x_gpio_attach(device_t dev)
> 	}
> 
> 	sc->dev = dev;
>-	avlpins = rt305x_gpio_init(dev);
>-
>-	/* Configure all pins as input */
>-	/* disable interrupts for all pins */
>-	/* TODO */
>-
>-	sc->gpio_npins = NGPIO;
>-	resource_int_value(device_get_name(dev), device_get_unit(dev), 
>-	    "pins", &sc->gpio_npins);
>-
>+	rt305x_gpio_pin_max(dev, &sc->gpio_npins);
>+
>+	/* Get the current function set */
>+	reg = rt305x_sysctl_get(SYSCTL_GPIOMODE);
>+	/* Enable function bits that are required */
>+	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
>+	    "function_set", &mask) == 0) {
>+		device_printf(dev, "function_set: 0x%x\n", mask);
>+		reg |= mask;
>+	}
>+	/* Disable function bits that are required */
>+	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
>+	    "function_clear", &mask) == 0) {
>+		device_printf(dev, "function_clear: 0x%x\n", mask);
>+		reg &= ~mask;
>+	}
>+	rt305x_sysctl_set(SYSCTL_GPIOMODE, reg);
>+
>+	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
>+	    "pinmask", &mask) != 0)
>+		mask = 0;
>+	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
>+	    "pinon", &pinon) != 0)
>+		pinon = 0;
>+	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
>+	    "pinin", &pinin) != 0)
>+		pinin = 0;
>+	device_printf(dev, "gpio pinmask=0x%x\n", mask);
>+
>+	/* Configure all pins, keep the loader settings */
>+	reg = bus_read_4(sc->gpio_mem_res, GPIO_REG(22, DIR)) << GPIO_BIT_SHIFT(22);
>+	reg |= bus_read_4(sc->gpio_mem_res, GPIO_REG(0, DIR));
> 	for (i = 0; i < sc->gpio_npins; i++) {
>+		if ((mask & (1 << i)) == 0)
>+			continue;
>+		snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
>+		    "pin %d", i);
>  		sc->gpio_pins[i].gp_pin = i;
>  		sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
>- 		sc->gpio_pins[i].gp_flags = 0;
>+ 		sc->gpio_pins[i].gp_flags = (reg & (1 << i)) ? GPIO_PIN_OUTPUT : GPIO_PIN_INPUT;
>+	}
>+
>+	/* Turn on the hinted pins or configure them as inputs. */
>+	for (i = 0; i < sc->gpio_npins; i++) {
>+		if ((pinon & (1 << sc->gpio_pins[i].gp_pin)) != 0) {
>+			rt305x_gpio_pin_setflags(dev, sc->gpio_pins[i].gp_pin, GPIO_PIN_OUTPUT);
>+			rt305x_gpio_pin_set(dev, sc->gpio_pins[i].gp_pin, 1);
>+		}
>+		if ((pinin & (1 << sc->gpio_pins[i].gp_pin)) != 0)
>+			rt305x_gpio_pin_setflags(dev, sc->gpio_pins[i].gp_pin, GPIO_PIN_INPUT);
> 	}
> 
> 	/* Setup reset pin interrupt */
>+	sc->reset_gpio = -1;
> 	if (TUNABLE_INT_FETCH("reset_gpio", &sc->reset_gpio)) {
> 		device_printf(dev, "\tHinted reset_gpio %d\n", sc->reset_gpio);
> 	}
> #ifdef	notyet
> 	if (sc->reset_gpio != -1) {
>-		rt305x_gpio_pin_setflags(dev, sc->reset_gpio, 
>+		rt305x_gpio_pin_setflags(dev, sc->reset_gpio,
> 		    GPIO_PIN_INPUT|GPIO_PIN_INVOUT|
> 		    GPIO_PIN_INVOUT|GPIO_PIN_REPORT);
> 		device_printf(dev, "\tUse reset_gpio %d\n", sc->reset_gpio);
> 	}
> #else
> 	if (sc->reset_gpio != -1) {
>-		rt305x_gpio_pin_setflags(dev, sc->reset_gpio, 
>+		rt305x_gpio_pin_setflags(dev, sc->reset_gpio,
> 		    GPIO_PIN_INPUT|GPIO_PIN_INVOUT);
> 		device_printf(dev, "\tUse reset_gpio %d\n", sc->reset_gpio);
> 	}
>@@ -622,5 +632,5 @@ static driver_t rt305x_gpio_driver = {
> };
> static devclass_t rt305x_gpio_devclass;
> 
>-DRIVER_MODULE(rt305x_gpio, obio, rt305x_gpio_driver, 
>+DRIVER_MODULE(rt305x_gpio, obio, rt305x_gpio_driver,
>     rt305x_gpio_devclass, 0, 0);
>diff --git a/sys/mips/rt305x/rt305x_gpio.h b/sys/mips/rt305x/rt305x_gpio.h
>index 8ce3ab5..79cdb2d 100644
>--- a/sys/mips/rt305x/rt305x_gpio.h
>+++ b/sys/mips/rt305x/rt305x_gpio.h
>@@ -1,4 +1,5 @@
> /*-
>+ * Copyright (c) 2015, Emmanuel Vadot <manu@bidouilliste.com>
>  * Copyright (c) 2010 Aleksandr Rybalko.
>  * All rights reserved.
>  *
>@@ -28,17 +29,19 @@
> #ifndef _RT305X_GPIO_H_
> #define _RT305X_GPIO_H_
> 
>-#define NGPIO			52
>-
>-#define RGMII_GPIO_MODE_MASK	(0x0fffULL<<40)
>-#define SDRAM_GPIO_MODE_MASK  	(0xffffULL<<24)
>-#define MDIO_GPIO_MODE_MASK   	(0x0003ULL<<22)
> #define JTAG_GPIO_MODE_MASK   	(0x001fULL<<17)
> #define UARTL_GPIO_MODE_MASK  	(0x0003ULL<<15)
> #define UARTF_GPIO_MODE_MASK  	(0x00ffULL<<7)
> #define SPI_GPIO_MODE_MASK    	(0x000fULL<<3)
> #define I2C_GPIO_MODE_MASK    	(0x0003ULL<<1)
> 
>+#if defined(RT3050F) || defined(RT3052F)
>+#define NGPIO			52
>+
>+#define RGMII_GPIO_MODE_MASK	(0x0fffULL<<40)
>+#define SDRAM_GPIO_MODE_MASK  	(0xffffULL<<24)
>+#define MDIO_GPIO_MODE_MASK   	(0x0003ULL<<22)
>+
> #define GPIO23_00_INT		0x00 /* Programmed I/O Int Status */
> #define GPIO23_00_EDGE		0x04 /* Programmed I/O Edge Status */
> #define GPIO23_00_RENA		0x08 /* Programmed I/O Int on Rising */
>@@ -78,10 +81,6 @@
> 	((g<24)?(1<<g):(g<40)?(1<<(g-24)):(1<<(g-40)))
> #define GPIO_BIT_SHIFT(g)	((g<24)?(g):(g<40)?(g-24):(g-40))
> 
>-#define GPIO_READ(r, g, n) 						\
>-	bus_read_4(r->gpio_mem_res, GPIO_REG(g, n))
>-#define GPIO_WRITE(r, g, n, v) 						\
>-	bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), v)
> #define GPIO_READ_ALL(r, n) 						\
> 	(((uint64_t)bus_read_4(r->gpio_mem_res, GPIO23_00_##n)) |	\
> 	(((uint64_t)bus_read_4(r->gpio_mem_res, GPIO39_24_##n)) << 24) |\
>@@ -91,6 +90,58 @@
> 	bus_write_4(r->gpio_mem_res, GPIO39_24_##n, (v>>24)&0x0000ffff);\
> 	bus_write_4(r->gpio_mem_res, GPIO51_40_##n, (v>>40)&0x00000fff);}
> 
>+#endif
>+
>+#ifdef RT5350F
>+#define NGPIO			28
>+
>+#define SPI_CS1_GPIO_MODE_MASK		(0x0001ULL<<27)
>+#define PHY_LED_GPIO_MODE_MASK   	(0x0003ULL<<22)
>+
>+#define GPIO21_00_INT		0x00 /* Programmed I/O Int Status */
>+#define GPIO21_00_EDGE		0x04 /* Programmed I/O Edge Status */
>+#define GPIO21_00_RENA		0x08 /* Programmed I/O Int on Rising */
>+#define GPIO21_00_FENA		0x0C /* Programmed I/O Int on Falling */
>+#define GPIO21_00_DATA		0x20 /* Programmed I/O Data */
>+#define GPIO21_00_DIR		0x24 /* Programmed I/O Direction */
>+#define GPIO21_00_POL		0x28 /* Programmed I/O Pin Polarity */
>+#define GPIO21_00_SET		0x2C /* Set PIO Data Bit */
>+#define GPIO21_00_RESET		0x30 /* Clear PIO Data bit */
>+#define GPIO21_00_TOG		0x34 /* Toggle PIO Data bit */
>+
>+#define GPIO27_22_INT		0x60
>+#define GPIO27_22_EDGE		0x64
>+#define GPIO27_22_RENA		0x68
>+#define GPIO27_22_FENA		0x6C
>+#define GPIO27_22_DATA		0x70
>+#define GPIO27_22_DIR		0x74
>+#define GPIO27_22_POL		0x78
>+#define GPIO27_22_SET		0x7C
>+#define GPIO27_22_RESET		0x80
>+#define GPIO27_22_TOG		0x84
>+
>+#define GPIO_REG(g, n)							\
>+	((g < 22) ? (GPIO21_00_##n) : (GPIO27_22_##n))
>+
>+#define GPIO_MASK(g)					\
>+	((g < 22) ? (1UL << g ) : (1UL << (g - 22)))
>+
>+#define GPIO_BIT_SHIFT(g)	(g < 22) ? (g) : (g - 22)
>+
>+#define GPIO_READ_ALL(r, n) 						\
>+	(((uint64_t)bus_read_4(r->gpio_mem_res, GPIO21_00_##n)) |	\
>+	(((uint64_t)bus_read_4(r->gpio_mem_res, GPIO27_22_##n)) << 22))
>+#define GPIO_WRITE_ALL(r, n, v) 					\
>+	{bus_write_4(r->gpio_mem_res,GPIO21_00_##n, v      &0x00ffffff);\
>+	bus_write_4(r->gpio_mem_res, GPIO27_22_##n, (v>>22)&0x0000ffff);}
>+
>+#endif
>+
>+
>+#define GPIO_READ(r, g, n) 						\
>+	bus_read_4(r->gpio_mem_res, GPIO_REG(g, n))
>+#define GPIO_WRITE(r, g, n, v) 						\
>+	bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), v)
> 
> #define GPIO_BIT_CLR(r, g, n) 						\
> 	bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), 			\
>@@ -100,8 +151,8 @@
> 	    bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) | GPIO_MASK(g))
> 
> #define GPIO_BIT_GET(r, g, n)						\
>-	((bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) >> 		\
>-	    GPIO_BIT_SHIFT(g)) & 1)
>+  ((bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) >>	\
>+    GPIO_BIT_SHIFT(g)) & 1)
> 
> #define GPIO_LOCK(_sc)		mtx_lock(&(_sc)->gpio_mtx)
> #define GPIO_UNLOCK(_sc)	mtx_unlock(&(_sc)->gpio_mtx)
>diff --git a/sys/mips/rt305x/rt305x_sysctl.c b/sys/mips/rt305x/rt305x_sysctl.c
>index 7c0d36d..693c51d 100644
>--- a/sys/mips/rt305x/rt305x_sysctl.c
>+++ b/sys/mips/rt305x/rt305x_sysctl.c
>@@ -1,4 +1,5 @@
> /*-
>+ * Copyright (c) 2015, Emmanuel Vadot <manu@bidouilliste.com>
>  * Copyright (c) 2010 Aleksandr Rybalko.
>  * All rights reserved.
>  *
>@@ -70,6 +71,7 @@ rt305x_sysctl_dump_config(device_t dev)
> 	    (val >> 24) & 0xff);
> 
> 	DUMPREG(SYSCTL_SYSCFG);
>+#if defined(RT3050F) || defined(RT3052F)
> 	if ( val & SYSCTL_SYSCFG_INIC_EE_SDRAM)
> 		printf("\tGet SDRAM config from EEPROM\n");
> 	if ( val & SYSCTL_SYSCFG_INIC_8MB_SDRAM)
>@@ -124,6 +126,7 @@ rt305x_sysctl_dump_config(device_t dev)
> 		SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT));
> 	DUMPREG(SYSCTL_GPIOMODE);
> #undef DUMPREG
>+#endif
> 
> 	return;
> }
>diff --git a/sys/mips/rt305x/rt305xreg.h b/sys/mips/rt305x/rt305xreg.h
>index 42a6c86..e242c4c 100644
>--- a/sys/mips/rt305x/rt305xreg.h
>+++ b/sys/mips/rt305x/rt305xreg.h
>@@ -1,4 +1,5 @@
> /*-
>+ * Copyright (c) 2015, Emmanuel Vadot <manu@bidouilliste.com>
>  * Copyright (c) 2010 Aleksandr Rybalko.
>  * All rights reserved.
>  *
>@@ -29,19 +30,15 @@
> #ifndef _RT305XREG_H_
> #define _RT305XREG_H_
> 
>-/* XXX: must move to config */
>-#define RT305X		1
>-#define RT305XF		1
>-#define RT3052F		1
>-#define __U_BOOT__	1
>-/* XXX: must move to config */
>-
> #ifdef RT3052F
> #define PLATFORM_COUNTER_FREQ	(384 * 1000 * 1000)
> #endif
> #ifdef RT3050F
> #define PLATFORM_COUNTER_FREQ	(320 * 1000 * 1000)
> #endif
>+#ifdef RT5350F
>+#define PLATFORM_COUNTER_FREQ	(360 * 1000 * 1000)
>+#endif
> #ifndef PLATFORM_COUNTER_FREQ
> #error "Nor RT3052F nor RT3050F defined"
> #endif
>@@ -60,16 +57,20 @@
> #define INTCTL_END 	0x100002FF
> #define MEMCTRL_BASE	0x10000300
> #define MEMCTRL_END 	0x100003FF /* SDRAM & Flash/SRAM */
>+#if defined(RT3050F) || defined(RT3052F)
> #define PCM_BASE 	0x10000400
> #define PCM_END 	0x100004FF
>+#endif
> #define UART_BASE 	0x10000500
> #define UART_END 	0x100005FF
> #define PIO_BASE 	0x10000600
> #define PIO_END 	0x100006FF
>+#if defined(RT3050F) || defined(RT3052F)
> #define GDMA_BASE 	0x10000700
> #define GDMA_END 	0x100007FF /* Generic DMA */
> #define NANDFC_BASE 	0x10000800
> #define NANDFC_END 	0x100008FF /* NAND Flash Controller */
>+#endif
> #define I2C_BASE 	0x10000900
> #define I2C_END 	0x100009FF
> #define I2S_BASE 	0x10000A00
>@@ -85,25 +86,45 @@
> #define ETHSW_END 	0x10117FFF /* Ethernet Switch */
> #define ROM_BASE 	0x10118000
> #define ROM_END 	0x10119FFF
>+#ifdef RT5350F
>+#define USB_OTG_BASE	0x10120000
>+#define USB_OTG_END	0x1012FFFF
>+#endif
> #define WLAN_BASE 	0x10180000
> #define WLAN_END 	0x101BFFFF /* 802.11n MAC/BBP */
>+#if defined(RT3050F) || defined(RT3052F)
> #define USB_OTG_BASE	0x101C0000
> #define USB_OTG_END 	0x101FFFFF
>+#endif
> #define EMEM_BASE 	0x1B000000
> #define EMEM_END 	0x1BFFFFFF /* External SRAM/Flash */
>+#ifdef RT5350F
>+#define BOOT_ROM_BASE	0x1C000000
>+#define BOOT_ROM_END	0x1C003FFF
>+#endif
>+#if defined(RT3050F) || defined(RT3052F)
> #define FLASH_BASE 	0x1F000000
> #define FLASH_END 	0x1FFFFFFF /* Flash window */
>+#endif
> 
> #define OBIO_MEM_BASE	SYSCTL_BASE
> #define OBIO_MEM_START	OBIO_MEM_BASE
>+#if defined(RT3050F) || defined(RT2052F)
> #define OBIO_MEM_END	FLASH_END
>-
>-
>+#endif
>+#ifdef RT5350F
>+#define OBIO_MEM_END	BOOT_ROM_END
>+#endif
> 
> /* System Control */
>-#define SYSCTL_CHIPID0_3 	0x00 /* 'R''T''3''0' */
>-#define SYSCTL_CHIPID4_7 	0x04 /* '5''2'' '' ' */
>+#define SYSCTL_CHIPID0_3 	0x00 /* 'R''T''3''0' for RT305X or 'R' 'T' '5' '3' for RT5350 */
>+#define SYSCTL_CHIPID4_7 	0x04 /* '5''2'' '' ' for RT305X or '5' '0' ' ' ' ' for RT5350 */
>+#ifdef RT5350F
>+#define SYSCTL_REVID		0x0C /* 0x1 0x1 - */ 
>+#endif
>+
> #define SYSCTL_SYSCFG		0x10
>+#if defined(RT3050F) || defined(RT3052F)
> #define SYSCTL_SYSCFG_INIC_EE_SDRAM		(1<<29)
> #define SYSCTL_SYSCFG_INIC_8MB_SDRAM		(1<<28) 
> #define SYSCTL_SYSCFG_GE0_MODE_MASK		0x03000000
>@@ -129,6 +150,17 @@
> #define SYSCTL_SYSCFG_SRAM_CS_MODE_WDOG_RST	1
> #define SYSCTL_SYSCFG_SRAM_CS_MODE_BT_COEX	2
> #define SYSCTL_SYSCFG_SDRAM_CLK_DRV		(1<<0) /* 8mA/12mA */
>+#endif
>+#ifdef RT5350F
>+#define SYSCTL_SYSCFG_PULL_EN			(1<<26)
>+#define SYSCTL_SYSCFG_SDR_PAD_DRV_MASK		0x0700000
>+#define SYSCTL_SYSCFG_SDR_PAD_DRV_SHIFT		20
>+#define SYSCTL_SYSCFG_SDR_PAD_DRV_0		0
>+#define SYSCTL_SYSCFG_SDR_PAD_DRV_1		1
>+#define SYSCTL_SYSCFG_SDR_PAD_DRV_2		2
>+#define SYSCTL_SYSCFG_USB0_MODE			(1<<10) /* 0 device / 1 host */
>+#define SYSCTL_SYSCFG_USB_PHY_EN		(1<<9)
>+#endif
> 
> #define SYSCTL_TESTSTAT		0x18
> #define SYSCTL_TESTSTAT2	0x1C
>@@ -142,6 +174,7 @@
> #define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_3NS_DELAY		3
> 
> #define SYSCTL_CLKCFG1		0x30
>+#if defined(RT3050F) || defined(RT3052F)
> #define SYSCTL_CLKCFG1_PBUS_DIV_CLK_BY2		(1<<30)
> #define SYSCTL_CLKCFG1_OTG_CLK_EN		(1<<18)
> #define SYSCTL_CLKCFG1_I2S_CLK_EN		(1<<15)
>@@ -152,6 +185,12 @@
> #define SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT 		(1<<6)
> #define SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK 		0x0000003f
> #define SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT 	0
>+#endif
>+#ifdef RT5350F
>+#define SYSCTL_CLKCFG1_SYSTICK_EN		(1<<29)
>+#define SYSCTL_CLKCFG1_PDMA_CSR_CLK_GATE_BYP	(1<<23)
>+#define SYSCTL_CLKCFG1_UPHY0_CLK_EN		(1<<18)
>+#endif
> 
> #define SYSCTL_RSTCTRL		0x34
> #define SYSCTL_RSTCTRL_ETHSW		(1<<23)
>@@ -176,10 +215,25 @@
> #define SYSCTL_RSTSTAT_SWSYSRST		(1<<2)
> #define SYSCTL_RSTSTAT_WDRST		(1<<1)
> 
>+#ifdef RT5350F
>+#define SYSCTL_CPU_SYS_CLKCFG	0x3C
>+
>+#define SYSCTL_CLK_LUT_CFG	0x40
>+
>+#define SYSCTL_CPU_CLK_AUTO_CFG	0x44
>+
>+#define SYSCTL_CPU_PLL_DYN_CFG	0x48
>+
>+#define SYSCTL_RF_RX_SD_CFG	0x58
>+
>+#endif
>+
> #define SYSCTL_GPIOMODE		0x60
>+#if defined(RT3050F) || defined(RT3052F)
> #define SYSCTL_GPIOMODE_RGMII_GPIO_MODE		(1<<9)
> #define SYSCTL_GPIOMODE_SDRAM_GPIO_MODE  	(1<<8)
> #define SYSCTL_GPIOMODE_MDIO_GPIO_MODE   	(1<<7)
>+#endif
> #define SYSCTL_GPIOMODE_JTAG_GPIO_MODE   	(1<<6)
> #define SYSCTL_GPIOMODE_UARTL_GPIO_MODE  	(1<<5)
> #define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_UARTF		(0<<2)
>@@ -193,8 +247,11 @@
> #define SYSCTL_GPIOMODE_SPI_GPIO_MODE    	(1<<1)
> #define SYSCTL_GPIOMODE_I2C_GPIO_MODE    	(1<<0)
> 
>+#if defined(RT3050F) || defined(RT3052F)
> #define SYSCTL_MEMO0		0x68
> #define SYSCTL_MEMO1		0x6C
>+#endif
>+
> 
> /* Timer */
> #define TIMER_TMRSTAT		0x00
>@@ -247,12 +304,15 @@
> #define IC_INT_ENA		0x34
> #define IC_INT_DIS		0x38
> 
>+#define IC_UDEV		19
> #define IC_OTG		18
> #define IC_ETHSW	17
> #define IC_UARTLITE	12
> #define IC_I2S		10
> #define IC_PERFC	9
>+#if defined(RT3050F) || defined(RT2052)
> #define IC_NAND		8
>+#endif
> #define IC_DMA		7
> #define IC_PIO		6
> #define IC_UART		5
>@@ -263,6 +323,9 @@
> #define IC_SYSCTL	0
> 
> #define IC_LINE_GLOBAL		(1<<31) /* Only for DIS/ENA regs */
>+#ifdef RT5350F
>+#define IC_LINE_UDEV		(1<<19)
>+#endif
> #define IC_LINE_OTG		(1<<18)
> #define IC_LINE_ETHSW		(1<<17)
> #define IC_LINE_UARTLITE	(1<<12)
>@@ -278,45 +341,7 @@
> #define IC_LINE_TIMER0		(1<<1)
> #define IC_LINE_SYSCTL		(1<<0)
> 
>-#define IC_INT_MASK		0x000617ff
>-
>-/* GPIO */
>-
>-#define GPIO23_00_INT		0x00 /* Programmed I/O Int Status */
>-#define GPIO23_00_EDGE		0x04 /* Programmed I/O Edge Status */
>-#define GPIO23_00_RENA		0x08 /* Programmed I/O Int on Rising */
>-#define GPIO23_00_FENA		0x0C /* Programmed I/O Int on Falling */
>-#define GPIO23_00_DATA		0x20 /* Programmed I/O Data */
>-#define GPIO23_00_DIR		0x24 /* Programmed I/O Direction */
>-#define GPIO23_00_POL		0x28 /* Programmed I/O Pin Polarity */
>-#define GPIO23_00_SET		0x2C /* Set PIO Data Bit */
>-#define GPIO23_00_RESET		0x30 /* Clear PIO Data bit */
>-#define GPIO23_00_TOG		0x34 /* Toggle PIO Data bit */
>-
>-#define GPIO39_24_INT		0x38
>-#define GPIO39_24_EDGE		0x3c
>-#define GPIO39_24_RENA		0x40
>-#define GPIO39_24_FENA		0x44
>-#define GPIO39_24_DATA		0x48
>-#define GPIO39_24_DIR		0x4c
>-#define GPIO39_24_POL		0x50
>-#define GPIO39_24_SET		0x54
>-#define GPIO39_24_RESET		0x58
>-#define GPIO39_24_TOG		0x5c
>-
>-#define GPIO51_40_INT		0x60
>-#define GPIO51_40_EDGE		0x64
>-#define GPIO51_40_RENA		0x68
>-#define GPIO51_40_FENA		0x6C
>-#define GPIO51_40_DATA		0x70
>-#define GPIO51_40_DIR		0x74
>-#define GPIO51_40_POL		0x78
>-#define GPIO51_40_SET		0x7C
>-#define GPIO51_40_RESET		0x80
>-#define GPIO51_40_TOG		0x84
>-
>-
>-
>+#define IC_INT_MASK		0x000717ff
> 
> #define GDMA_CHANNEL_REQ0	0
> #define GDMA_CHANNEL_REQ1	1 /* (NAND-flash) */
>diff --git a/sys/mips/rt305x/std.rt305x b/sys/mips/rt305x/std.rt305x
>index c7212a2..9a1620b 100644
>--- a/sys/mips/rt305x/std.rt305x
>+++ b/sys/mips/rt305x/std.rt305x
>@@ -5,3 +5,4 @@ files	"../rt305x/files.rt305x"
> 
> cpu		CPU_MIPS4KC
> 
>+options		RT3050
>diff --git a/sys/mips/rt305x/std.rt5350 b/sys/mips/rt305x/std.rt5350
>new file mode 100644
>index 0000000..934a5ea
>--- /dev/null
>+++ b/sys/mips/rt305x/std.rt5350
>@@ -0,0 +1,8 @@
>+# $FreeBSD$
>+# Standard include file for RT5350 SoC
>+
>+files	"../rt305x/files.rt305x"
>+
>+cpu		CPU_MIPS4KC
>+
>+options		RT5350F

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Attachments on bug 201958: 159354