In the file `sys/boot/uboot/lib/libuboot.h:47` it says: #define PKTALIGN 32 Unfortunately this causes an error "CACHE: Misaligned operation at range [xxx, xxx]" since this is not enough to aligned to the data cache in ARMv7 cpus (such as the AM335x). This value should be changed to reflect the setting in U-Boot of `CONFIG_SYS_CACHELINE_SIZE` which is determined by `SYS_CACHE_SHIFT_X` define in the U-Boot file `arch/arm/Kconfig`. I have temporarily changed the line to: #define PKTALIGN 64 This change may be sufficient given that the block of memory being aligned is `ETHER_MAX_LEN` in size (so 1518 bytes) this only wastes ~2% storage. This will fail however for CPUs with a CACHELINE_SIZE of 128 (currently only listed as the ThunderX and the Uniphier).
A commit references this bug: Author: ian Date: Sun Dec 10 23:06:45 UTC 2017 New revision: 326754 URL: https://svnweb.freebsd.org/changeset/base/326754 Log: When building for arm arches, set PKGALIGN to the max cache line size supported by the arch, to meet u-boot's requirement that I/O be done in cache-aligned chunks. PR: 223977 Changes: head/stand/uboot/lib/libuboot.h
A commit references this bug: Author: ian Date: Mon Dec 18 17:17:07 UTC 2017 New revision: 326934 URL: https://svnweb.freebsd.org/changeset/base/326934 Log: MFC (conceptually) r326752, r326754: This is a direct commit to 11-stable, because the code has moved and the directories have been restructured in 12-current, but it just hand- applies the same patches to the corresponding files in their old locations. r326752: Save and restore r9 register in arm ubldr. In old gcc 4.2, r9 was a callee- saved register, but in arm EABI it may be either callee-saved or dedicated to some special purpose (such as a TLS pointer). It appears clang does not treat it as a callee-saved register (instead using it as another work register, similar to r12). Another important side effect of these changes is that saving an extra register in the push/pop statements keeps the stack aligned to an 8-byte boundary during the self_reloc() call, as it always should have been. As stated in the PR... Essentially the important caller-saved registers are pushed (r0, r1, r9, lr) before the relocation call, and popped after. Then r8/r9 are saved as usual for the syscall trampoline, and lr is stored in r8 (now free) as a callee-saved value before calling into `main`. The call to `main` can no longer be a tail call because we must restore r9 especially after main returns (although since we have used r8 to hold lr we must also restore this). r326754: When building for arm arches, set PKTALIGN to the max cache line size supported by the arch, to meet u-boot's requirement that I/O be done in cache-aligned chunks. PR: 223977 224008 Changes: stable/11/sys/boot/arm/uboot/start.S stable/11/sys/boot/uboot/lib/libuboot.h