Hi, Is there a DMA alignment requirement for genet driver's TX/RX buffer? In gen_bus_dma_init(), genet driver requires the TX/RX buffer to be 4 bytes aligned. However, gen_newbuf_rx() fetches a mbuf cluster, then trims the first two bytes of the mbuf cluster. My understanding is that the RX buffer will be 2 bytes aligned but might not be 4 bytes aligned. I understand that the DMA stack will handle this misalignment using something like a bounce buffer. Since there isn't a document for the bcm ethernet controller online, I am curious about the reason why genet driver does not enforce the allocated mbuf to be 4 bytes aligned. In TX, genet driver does not know the starting address of mbuf passed from the upper layer. Is it possible that the genet driver is also compatible with other alignment constraints, like 1, 2, or 32 byte(s)? Thanks, Jiahao
CC'ing Mike Karels, who imported the driver. I suspect that genet does this so that the IP header is 4-byte aligned, since that could make accesses to header fields more efficient. But indeed, it's rather strange that rx_buf_tag is defined with an alignment of 4. I'd expect that to result in extra copying.
At the time this driver was done, IP headers had to be 4-byte-aligned on arm64. The two-byte adjustment was to make the Ethernet header end on a 4-byte alignment. I'm not aware of anything that forces this through a bounce buffer. If there is such a thing, this should probably be reconsidered. Apparently now IP and TCP headers do not need to be 4-byte aligned, although I don't know specifics.